Restrictive Design Rules, Take Two

By Ed Sperling

For the past couple of years, restrictive design rules have been looming over advanced process nodes as the best way to get a chip out the door with minimal re-spins, on schedule and for the least amount of money.

Even with immersion technology, 193nm wavelengths mean the laser beam is entirely too large to create the masks used to create complex systems on chip at 32nm and below. It’s like trying to operate on a patient with a dull butter knife rather than a razor-sharp scalpel. And with extreme ultraviolet and e-beam still years away from commercial availability—and some doubts lingering about whether they ever will be ready—restrictive design has emerged as a requirement for foundries such as TSMC.

But exactly how tightly those rules will become is unknown at this point. Just as many predicted the end of Moore’s Law at 1 micron because of lithography limitations, it’s hard to predict where there will be new breakthroughs. Self-assembly and carbon materials may entirely change the way chips are created at future process nodes, for example. But for the immediate future—32/28nm, 22nm and all the way down to 15nm—most scientists and engineers are looking at evolving existing technology rather than radical breakthroughs.

One such tool is computational scaling, which uses complex formulas to create masks rather than actually etching them. While it doesn’t entirely eliminate the need for restrictive design rules, it certainly raises questions about just how onerous those rules will become.

“As an integrated systems company we still have to sit down each generation with the process guys and figure out who’s better off taking the pain,” said Brad McCredie, an IBM fellow and vice president of the company’s Power Technology group. “At 65nm, it was all about shapes so we could print on the right grid. With design restrictions, it’s easier to print the shape. But you still have to have conversations like that at every node.”

Most chipmakers and foundries have come to the conclusion that more regular shapes in the design, as well as more regular spacing of those shapes, helps improve design success with minimal re-spins. There likely will be additional restrictions in the future, as well, such as what can be added where and when in a design.

“We will have convergences like that at every node,” said McCredie. “There is no panacea showing up. It’s getting tougher and tougher for CA (the first contact layer in chip design) and M1 (first metal layer in the chip).”

IBM introduced computational scaling last fall for the 22nm process node, offering one more tool to help in design for manufacturability. An IBM paper published in September 2008 says there is “tremendous pressure on the design process and the mask technology that need to overcome the two-dimensional limitations of the lithographic process.” The paper noted that the amount and complexity of the processing will be “very large, requiring source/mask optimization and optimized design rules.”

IBM also inked a deal with Mentor Graphics to jointly develop some of the tools around computational scaling, based upon Mentor’s Calibre platform. Mentor introduced computational optical correction and acceleration last year.

But IBM and Mentor aren’t the only ones wrestling with difficult processes at future process nodes. All of the major chipmakers are dealing with the same issues, and all of the commercial foundries are struggling to balance the needs for creativity in design with the ability to get chips into production in ever-shorter market windows. Tom Quan, TSMC deputy director, said that at 40nm there will be some rules for design, but he said the bank of rules will increase at 28nm and again at 22nm.

“When you have restrictive rules for layout you increase your predictability,” Quan said. “For the layout designer, that means less freedom.”

For the chip companies, it also means less differentiation in hardware and significantly more in software. But a lot of very smart people are working on the problem, even if they don’t have a clear answer at this point.