Increased complexity in process technology and litho delays are forcing equipment companies to get much more aggressive about technology and market approaches.
The perennial uncertainty surrounding EUV lithography and complications stemming from the most advanced nodes are creating a domino effect across the semiconductor industry.
Rather than stalling the market, though, which is what happened with the transition to 20nm, vendors now are accelerating their product rollouts and adjusting business plans to capitalize on those delays. That includes making their products run faster to compensate for the impact of multi-patterning or an underpowered EUV, rolling out new equipment on or ahead of schedule for faster and more effective inspection, etch or processing, and flattening their business models to react much more quickly to market changes.
This is a far different climate than the one experienced at 20nm, when faced with a leaky process, chipmakers took time out to evaluate everything from finFETs and double patterning with colors to new packaging options and materials such as FD-SOI. The move to the next node is every bit as complicated, but there are fewer unanswered questions about the benefits of moving in various directions—forward to finer geometries, upward into stacked die, or staying put with new materials or process flavors at existing process nodes. There also is less uncertainty about how fast wafers can be processed using current lithography, prompting equipment makers to compensate by improving throughput on own equipment or with combinations of more tightly integrated equipment. As a result, the equipment market is no longer wracked with uncertainty. Instead, it’s more like a feeding frenzy, where market share can be gained or lost based on the ability to react to problems elsewhere in the flow.
Case in point: In a briefing to analysts earlier this month, Martin Anstice, president and CEO of Lam Research, said the company is revising all cycle times and lead times downward. “This is a big component of yield,” he said. “The market share momentum over 2015 to 2016 will be more than from 2014 to 2015.”
Anstice added that the challenges of complying with Moore’s Law are increasing, requiring scale as well as a different way of looking at problems. “You have to innovate not just around products and technology, but around the business model.”
Lam isn’t alone in this—far from it, in fact. Companies on every side of the industry, and in particular very large companies, are viewing these hiccups as an opportunity to either solidify their market share or add to it. In a recent speech, Rick Wallace, president and CEO of KLA-Tencor, shed light on the company’s restructuring this year from 14 divisions down to 3. “The reason for that is the industry dynamics have changed,” he said. “We are going to focus on solutions, not just tools. We still believe in the need for best-in-class tools, but increasingly our customers are using multiple tools to support their needs.”
Wallace noted that with an increase in development costs, that also provides the ability to move resources from one platform to another more easily. In the past, the most profitable divisions could overinvest, while those with lower profits might not be able to invest enough.
Applied Materials‘ president and chief executive, Gary Dickerson, voiced a similar perspective in his presentation to analysts. He said the migration from planar to finFETs, and from 2D NAND to 3D NAND are inflection points for the semiconductor industry. “Those technologies, and to enable these major inflections, are bigger than what we’ve ever seen in this industry. FinFET, and the changes in the transistor, are bigger than what we’ve ever seen. The transition of 3D NAND in the memory market is the biggest change in decades.”
Dickerson said there are two things driving Applied’s business—fast cycle times in terms of technology, and really big changes involving mobility, automotive, IoT and wearable electronics.
“You either hit these windows or you’re out,” he said. “We moved $400 million of investments in the company and into these opportunities, and into products, as we enable our customers in these major inflections…We’ve moved money from our overhead groups, and also from low performing businesses, into areas that move the needle for our customers.”
These changes mirror, to some extent, what has been going on in the EDA industry over the past 12 to 18 months. The whole concept of “shift left”—doing more concurrently rather than sequentially and earlier in the design cycle—has become a mantra in the EDA tools and IP market. Verification of complex circuitry and software development is taking an increasing amount of time, and the only way to compensate for that is to start earlier. The result has been a huge surge in emulation hardware, virtual prototyping of software, and hardware-accelerated everything. In fact, there is so much momentum that established EDA companies have been swallowing startups at an accelerated rate in an effort to get a jump on new opportunities.
That kind of consolidation is more difficult in the equipment space, where companies are larger and deals are subject to much more scrutiny by government agencies. But the trends that have prompted these acquisitions are complementary—more communication across groups that historically have not worked together.
“We’ve been working early on with multiple research organizations on future processes,” said Juan Rey, senior director of engineering for Calibre at Mentor Graphics. “You need to do more with future nodes, and on one side of that is the need for more guidance. So with DSA, for example, you need to focus on structures that are acceptable for the design community. The committee developing DSA was not aware of this.”
While the semiconductor industry has talked extensively about a virtual IDM model, the reality is that most work was done independently outside of pre-competitive process research. Even work that supposedly was done in sync was done separately or sequentially. Increasingly, it has to be done concurrently or chipmakers will miss their shrinking market windows.
“There isn’t much time, so you have to interact with more companies at the same time,” said Rey. “You also have to develop solutions for multiple processes without knowing which one ultimately will be used. DSA still has issues concerning what are the patterns that can be safely manufactured. And EUV still has power limitations that affect the throughput.”
The well-publicized problems with EUV echo across the manufacturing process, largely because it was the best bet for continuing to shrink features down to at least 10nm. Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries, said the cycle time is more than doubled with double patterning, which requires two litho steps and three etch steps. And that’s just the beginning of fab throughput issues.
“Everything else is two times more than single patterning, as well,” Kye said. “Manufacturing throughput is just one part. There is process setup time. There also is queue time, which slows production. So double patterning is more than two times more expensive than single patterning—it’s roughly 2.4 times as expensive. It also affects how you utilize throughput, so you can double your throughput or double your capacity.”
He said EUV remains the best option. “If it works, everyone will be happy,” he said.
And if it doesn’t, there are other options, and no shortage of companies looking to capitalize on the delay.
Slicing up the process
But even EUV will require double patterning at 7nm. Gary Patton, GlobalFoundries’ CTO, said 10nm will be a long-lived node even for advanced chipmakers. “There are a lot of value propositions being built around that node,” he said.
How many companies will move to 7nm and 5nm is uncertain, and Intel’s recent 10nm delay has raised some concerns in that direction. The path forward is hardly straightforward. There isn’t even agreement on what type of transistor will be used at upcoming nodes. Complicating this is that all of the major foundries now offer multiple slices of the same process node, depending up market segment—ultra low power, high performance, lower cost, balanced performance and power, as well as some with new materials such as 28nm and 22nm FD-SOI. And there is work underway at 10nm, 7nm and 5nm with at least as many process slices. The assumption is that each of them will try to win business with better power and performance, but if that doesn’t work they will compete on price.
What works best and for whom may be very individual decisions, and as foundries grow further apart on their processes and IP ecosystems at more advanced nodes, those decisions are even fuzzier. But at least for equipment makers, the path forward is clear. If they can provide enough of a value proposition to move chipmakers forward, they stand to gain market share and more business. And if they fail to execute, there will be companies ready to capitalize on their mistakes.
—Mark LaPedus contributed to this report.