Design and actual measurement of a 130 nm test chip for reducing the digital switching noise in synchronous circuits.
This paper outlines the design and measurement of a 130 nm test chip named SCREAMER for reducing the digital switching noise in synchronous circuits. Clock latency scheduling has been investigated as a means to optimize switching noise in the frequency domain through PDN simulation. Integrated in parallel on the chip are four instances of a test design, each addressing a distinct strategy of clock scheduling for on-chip clock tree synthesis. These strategies target two desired frequency traits, namely reduction near the design clock frequency, as well as reduction near the GSM-850 band. The effectiveness of the methodologies is assessed in a comparative study through on-chip substrate noise measurements, demonstrating that marked reductions in both target traits are achievable.
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