Stacked Die Politics, Technology And Tools

The path to stacking die may look fairly straightforward, but reality is somewhat different. There is a battle raging between foundries and OSATs over who will actually stack and package the die. There is new technology being created that could change the economics of how these die go together. And there is debate about just how ready the tools are to make all of this happen.

All of this is affecting the rollout schedule, pricing and how quickly tools are updated to deal with issues. While an analysis by Gartner showed that die stacking will become much more prevalent after 14nm—the cost of developing chips at 10nm, coupled with lower yields will make it much more attractive—there are questions about whether full using through-silicon vias and extremely thin die in a single package will be ready by then.

A new dimension
A large part of the reasoning behind this is foundries and OSATs are picking their battles carefully. Equipment to handle thin die and package them together is extremely expensive, and if there are not enough customers then the amortization of that equipment will take much longer.

From a business standpoint, that approach doesn’t make sense for most applications. In fact, the companies that likely would use full 3D are the same ones that would otherwise follow down to the most advanced nodes. They are the high-volume, high-performance, form-factor limited mobile players, and possibly some defense contractors that can afford to pay for low-volume, highly engineered devices.

Contrast that with 2.5D, which already is being used by Xilinx and Altera to improve yields with smaller die sizes. The packaging approach promises significant improvements in performance, energy efficiency, and time to market because analog IP can be built at older process technology and connected together.

Samuel Wang, vice president of research at Gartner, said the real push will begin after 14nm, when yields decline and the cost of developing complex SoCs—which includes everything from high-mobility materials to complex verification and test and increased NRE costs—rise to the point where stacking die becomes a viable and cost-effective alternative.

At that point—and both EDA companies and foundries already are working on 10nm process technology and tools—2.5D becomes much more attractive, particularly for heterogeneous chip integration. That point has been echoed by researchers such as Imec, as well as OSATs such as ASE and Amkor.

“Wide I/O memory, which was the start of all things 3D with respect to TSV, was very active through 2011, significantly slowed for a few years, and recently became active again. The activity has re-emerged in Wide I/O 2 format, which uses less power, adds more bandwidth, and allows data rates well beyond LP DDR5,” said Ron Huemoeller, senior vice president of advance product development at Amkor. “Simultaneously, interest and activity in 2.5D has continued to grow as it is easier to justify from a cost perspective at the system level and you are not risking very expensive silicon by placing the TSV’s inside near the transistors. Unfortunately, the original introduction of 2.5D through Xilinx with the deconstruction of a monolithic die was not enough to move the market, but the second wave of products will be. SoC partitioning will be one path and disparate die integration will be another. You will also see emergence of heterogeneous die integration within a single package involving memory. Die that traditionally existed in separate packages on the same motherboard (on board memory), will now coexist within the same package due to HBM (high bandwidth memory). This allows for reduction in the overall size and layer count of the motherboard which effectively results in system level cost savings. You’re going to see this transition over the next two to three years.”

Interest in 2.5D approach has been gathering steam and adherents, although somewhat quietly. The same cannot be said for the initial approaches to full 3D-ICs, outside of very specific markets such as memory.

“In the last two years, a few roadblocks have cropped up in 3D TSVs that now appear insurmountable,” said Raj Pendse, chief marketing officer at STATS ChipPAC. “From a design perspective, you’re dumping a large number of TSVs into silicon, which is a significant loss of real estate. This is not on the perimeter of the chip. It’s in the center, and it’s cost-prohibitive. The technology is also very node-specific, which would mean the development cycle lags behind the silicon.”

New approaches
But all of this is assuming that 3D ICs are a fixed approach. They’re not, and some novel techniques are being created to simplify the whole packaging and testing process.

One of the more intriguing ones to surface comes from a startup called ThruChip Communications, which proposes a wireless solution based upon inductive coupling using small coils to move signals between die rather than relying on TSVs. (See related article here.)The big advantage is that it eliminates the stress and thermal issues associated with drilling TSVs through thin die, and it makes layout of the die simpler.

“Cost is the killer in 3D ICs,” said Dave Ditzel, ThruChip’s CEO. “People would pay 5% more for stacked die, but no one will pay 50% to 2X more. And because this is wireless and a lot of design already has been done at these processes, you get the same yield as you would under a normal chip. There are standard layers of metal and no additional circuitry. The yield issue is more about stacking, not the die.”

Ditzel noted the silicon can be thinned now down to 4 microns, rather than the 50 microns originally proposed, allowing the die itself to do the power distribution. “With a super-thin die, you can do power distribution in a new way. Plus, the area for the inductors can go down about 100X, which can lead to reductions in die size.”

Another approach is a hybrid of 3D stacks in a 2.5D configuration, possibly using photonics. The likely scenario here is for stacked memory connected with through-silicon vias, notably the Hybrid Memory Cube architecture, in addition to an interposer and/or optical communication.

“Memories suppliers will lead the way with stacked die production for applications like HMC, as will opto-electronics at a lower volume,” said Dan Leung, director of packaging and assembly at Open-Silicon. “For memory suppliers, the bandwidth increase for stacked die is very large. However, relatively speaking, the number of I/O’s is lower as is the device power. Lastly, they have control over both their memory die and the controller chip necessary in the memory stack. Standards have already been established, and sampling has been promised shortly. For opto-electronics, the ability to combine dies from two different technologies is very important. Conversion from optical signaling to digital signaling within the same unit at a very high speed is key to their growth.”

There also are ways to extend the package-on-package architecture using interposers that more than double the pin count. Currently, PoP approaches use between 200 to 300 pins, said STATS ChipPAC’s Pendse. With high-density organic substrates and fan-out packaging, the pin count can be increased to 500 to 1,000, which essentially doubles the bandwidth.

“This gives you headroom for a reasonable cost, Pendse said. “And 2.5D allows you to extend the architecture further. It provides better performance than PoP, and if you partition the silicon on large dies, you can actually decrease the overall cost.”

Where the gaps are
Economics is the real impediment to full 3D of any sort at this point. If new approaches kick in, there may be movement toward 3D stacking. But part of this also requires a different way of looking at design in total—basically reconfiguring silos of cost centers within a company.

“The technology of 3D ICs is not mature enough to reduce cost at this point,” said Brandon Wang, engineering group director at Cadence. “Initially companies were considering TSVs as an additional cost. Some market firms have been tracking TSV shipments and TSVs are there. But the other requirement is thinning of wafers, where the cost is yield drop. That’s reflected in the overall cost. Even with economies of scale, if that is not resolved there won’t be much cust reduction. But there will still be a performance improvement and energy reduction. There is a power benefit of more than 50%, performance increases, and there are fewer signal integrity issues. So the measurements are different.”

That’s clearly not the general perception, though.

“People got cold feet when they looked at the cost because of yield and the complexity of the work flow,” said Mike Gianfagna, vice president of marketing at eSilicon . “There are still multisourcing and new assemble issues with 2.5D, but at least you’re not taking paper-thin silicon, drilling it full of holes, and dealing with the thermal and mechanical issues.”

If the economics do work, then attention will be turned to filling in the missing pieces. One piece in particular, that will need to be corrected is pathfinding, a term that has been used in EDA for making comparisons between different IP and packaging approaches at the architectural level.

“What’s needed are tools to do the tradeoffs across the different packaging options, and to do that you need to understand the chip, the package and board level parts,” said John Park, methodology architect for advanced packaging technologies at Mentor Graphics. “You also need to understand the connectivity piece with this. Connectivity management will be a huge issue. Right now you may have 60 different power domains on an SoC and only five on a board. And you need to understand with assembly and optimization how many layers you can cut out of a design, so maybe you route through three layers instead of five.”

And finally, what is the last business hurdle to overcome to allow companies to start designing into TSV architectures? “What’s really needed here is courage,” said Amkor’s Huemoeller. “Platform decisions like this can easily be considered career decisions.”

To view part one of this report, click here.