Five Trends In IC Packaging


At one time, chip packaging was an afterthought. Chipmakers were more worried about IC design. Packaging was considered a mere commodity, which was simply used to house the design. More recently, though, chip packaging has become a hot topic. The IC design is still important, but packaging is a key part of the solution. In fact, the industry can go down two paths. The traditional way is t... » read more

What’s Next For Atomic Layer Etch?


After years in R&D, several fab tool vendors last year finally began to ship systems based a next-generation technology called atomic layer etch (ALE). [getkc id="284" kc_name="ALE"] is is moving into 16/14nm, but it will play a big role at 10/7nm and beyond. The industry also is working on the next wave of ALE technology for advanced logic and memory production. Used by chipmakers fo... » read more

Tech Talk: Near-Threshold Power


Lauri Koskinen, CTO and founder of Minima Processor, and Ron Moore, vice president of marketing at ARM, talk about near-threshold computing, dynamic power and margining, and how these techniques can extend battery life and reduce energy consumption. https://youtu.be/BhiNFe4NYQU » read more

Lots Of Little Knobs For Power


Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

Tech Talk: Pseudo SRAM


eSilicon's Kar Yee Tang explains how to improve performance at 10/7nm without affecting power and area. https://youtu.be/4LI1pBLxxS4 » read more

New Power Concerns At 10/7nm


As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult. There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers ... » read more

Noise Abatement


[getkc id="285" kc_name="Noise"] is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes more complex? For some, the answer is a very strong yes, while for ot... » read more

Challenges Mount For Photomasks


Semiconductor Engineering sat down to discuss photomask technologies with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); Banqiu Wu, principal member of the technical staff and chief technology officer of the Mask and TSV Etch Division at [getentity id="22817" e_name="Applied Materials"]; Weston Sousa, general manager of the Reticle Products Division at [getentity id="22876" commen... » read more

Node Warfare?


By Mark LaPedus & Ed Sperling GlobalFoundries uncorked a 12nm finFET process, which the company said will provide a 15% increase in density and more than 10% improvement in performance over the foundry's existing 14nm process. This is GlobalFoundries' second 12nm process. It announced a 12nm FD-SOI process called 12FDX last September, although it first mentioned a 12nm process back in J... » read more

Power Modeling and Analysis


Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], chief technology officer at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], chief executive officer for [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021"... » read more

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