Overcoming The Limits Of Scaling

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

How Many Nanometers?

What’s the difference between a 10nm and a 7nm chip? That should be a straightforward question. Math, after all, is the only pure science. But as it turns out, the answer is hardly science—even if it is all about numbers. Put in perspective, at 65nm, companies defined the process node by the half pitch of the first metal layer. At 40/45nm, with the cost and difficulty of developing n... » read more

To 10nm And Beyond

Hong Hao, senior vice president of the foundry business at Samsung Semiconductor, sat down with Semiconductor Engineering to discuss the future direction of transistors, process technology, lithography and other topics. What follows are excerpts of those conversations. SE: Samsung recently rolled out its 10nm finFET technology. It appears that Samsung is the world’s first company to ship 1... » read more

10nm FinFET Market Heats Up

The 10nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes. Not long ago, Intel announced its 10nm finFET process, with plans to ramp up the technology in 2017. Then, TSMC recently introduced its 10nm process, with plans to move into production by the fourth quarter of 2016. Now, Samsung Electronics said that it has commenced mass... » read more

Mask Maker Worries Grow

Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the [getkc id="265" kc_name="photomask"] are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fab... » read more

Hitting The Power Integrity Wall At 10nm

At 10nm and beyond, the breakdown of some historic trends tied to Moore's Law is making it harder to fully harvest the benefits of scaling semiconductor technologies. Underlying the power, performance and area benefits of scaling are technological challenges that must be solved in order to make the semiconductor products a profitable business. Power-related challenges are among the most pres... » read more

Optimization Challenges For 10nm And 7nm

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032" e... » read more

Stepping Back From Scaling

Architectures, packaging and software are becoming core areas for semiconductor research and development, setting the stage for a series of shifts that will impact a large swath of the semiconductor industry. While there is still demand from the largest chipmakers for increased density at the next process node, the underlying economics for foundries, equipment vendors and IP developers are f... » read more

Deeper Inside Intel

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

Fins And Wires – How Do We Get To 5nm?

As the industry moves beyond 10nm to the 7nm and 5nm nodes, fundamental shifts are needed to address scaling challenges. Among the priority concerns driving industry changes, particularly with respect to materials and architecture, is the impact on transistor performance from rising parasitic resistance and parasitic capacitance or RC. I spoke about this industry dilemma recently at the SEMICON... » read more

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