tag: 22nm

Foundries Prepare For Battle At 22nm
By Mark LaPedus - 19 Nov, 2018 - Comments: 0

After introducing new 22nm processes over the last year or two, foundries are gearing up the technology for production—and preparing for a showdown. GlobalFoundries, Intel, TSMC and UMC are developing and/or expanding their efforts at 22nm amid signs this node could generate substantial business for applications like automotive, IoT and wireless. But foundry customers face some tough choic... » read more

Design Compliant Source Mask Optimization (SMO)
By PDF Solutions - 20 Sep, 2018 - Comments: 0

Source Mask Optimization (SMO) is required to extend the use of 193 water immersion lithography to the 22nm technology node. Although SMO is being aggressively pushed in volume production the layout design implications of this technology have not been openly discussed. In this paper, the impact of layout design style on simultaneous SMO of Logic and SRAM is studied. In particular the improvemen... » read more

GF Puts 7nm On Hold
By Mark LaPedus - 27 Aug, 2018 - Comments: 6

GlobalFoundries is putting its 7nm finFET program on hold indefinitely and has dropped plans to pursue technology nodes beyond 7nm. The moves, which mark a major shift in direction for the foundry, involve a headcount reduction of about 5% of its worldwide workforce. At the same time, the company is also moving its ASIC business into a new subsidiary. As a result of GlobalFoundries’ ann... » read more

Mixed Outlook For Semi Biz
By Mark LaPedus - 25 Jul, 2018 - Comments: 0

Both the IC and fab equipment industries have been enjoying a boom cycle for some time, but they could be facing speed bumps and possibly turbulence in the second half of this year and into 2019. In the first half of 2018, the industry was fueled by the momentum carried over from 2017. DRAM prices remained relatively high, which contributed to the revenue growth in the overall IC industry. M... » read more

22nm Process Technology
By Ed Sperling - 19 Jul, 2018 - Comments: 0

Jamie Shaeffer, senior director of product line management at GlobalFoundries, talks about how FD-SOI compares with bulk technologies, where it will be used and why, and future stacking options. https://youtu.be/2i7GJRxcNRs » read more

The Power Of De-Integration
By Ed Sperling - 17 May, 2018 - Comments: 0

The idea that more functionality can be added into a single chip, or even into a single system, is falling out of vogue. For an increasing number of applications, it's no longer considered the best option for boosting performance or lowering power, and it costs too much. Hooman Moshar, vice president of engineering at Broadcom, said in a keynote speech at Mentor's User2User conference this w... » read more

Chipmakers Look Beyond Scaling
By Ed Sperling - 17 May, 2018 - Comments: 1

Gary Patton, CTO of GlobalFoundries, sat down with Semiconductor Engineering to discuss the rollout of EUV, the rising cost of designing chips at the most advanced nodes, and the growing popularity of 22nm planar FD-SOI in a number of markets. What follows are excerpts of that conversation. SE: You've just begun deploying EUV. Are you experiencing any issues? Patton: It's a very complicat... » read more

A New Memory Contender?
By Mark LaPedus - 02 Jan, 2018 - Comments: 1

Momentum is building for a new class of ferroelectric memories that could alter the next-generation memory landscape. Generally, ferroelectrics are associated with a memory type called ferroelectric RAMs (FRAMs). Rolled out by several vendors in the late 1990s, FRAMs are low-power, nonvolatile devices, but they are also limited to niche applications and unable to scale beyond 130nm. While... » read more

Foundry Challenges in 2018
By Mark LaPedus - 27 Dec, 2017 - Comments: 6

The silicon foundry business is expected to see steady growth in 2018, but that growth will come with several challenges. On the leading edge, GlobalFoundries, Intel, Samsung and TSMC are migrating from the 16nm/14nm to the 10nm/7nm logic nodes. Intel already has encountered some difficulties, as the chip giant recently pushed out the volume ramp of its new 10nm process from the second half ... » read more

Body Biasing For Analog Design
By Fraunhofer IIS/EAS - 13 Dec, 2017 - Comments: 0

This paper presents the practical application of body biasing control of ultra-deep submicron FD-SOI technologies for analog and mixed-signal designs. The body biasing control is dedicated for dynamic control of the trade- off between speed vs. power consumption for advanced digital circuits. However, in this work we focus on trading-off and improvement of analog circuit performances. Three dif... » read more

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