tag: 3D DRAM

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development
By Coventor - 17 Apr, 2024 - Comments: 0

Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development ... » read more

3D Memory Structures: Common Hole And Tilt Metrology Techniques and Capabilities
By Technical Paper Link - 03 Jun, 2023 - Comments: 0

A technical paper titled "Inline metrology of high aspect ratio hole tilt and center line shift using small-angle x-ray scattering" was published by researchers at Bruker Nano and Lam Research. Abstract: "High aspect ratio (HAR) structures found in three-dimensional nand memory structures have unique process control challenges. The etch used to fabricate channel holes several microns deep... » read more

Devices And Transistors For The Next 75 Years
By Laura Peters - 16 Feb, 2023 - Comments: 0

The 75th anniversary of the invention of the transistor sparked a lively panel discussion at IEDM, spurring debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and what will be the next great memory architecture.[1] Industry veterans from the memory, logic, and research communities see high-NA EUV production, NAND flash with 1,000 layers, and hybrid bon... » read more

Wafer Cleaning Becomes Key Challenge In Manufacturing 3D Structures
By Adele Hars - 20 Oct, 2022 - Comments: 0

Wafer cleaning, once a rather mundane task as simple as dipping wafers in cleaning fluid, is emerging as one of the top major engineering challenges for manufacturing GAA FETs and 3D-ICs. With these new 3D structures — some on the horizon but some already in high-volume manufacturing — semiconductor wafer equipment and materials suppliers in the wet cleaning business are at the epicenter... » read more

Week In Review: Manufacturing, Test
By Linda Christensen - 15 Apr, 2022 - Comments: 0

Photonic Chips Go Big In Europe PhotonDelta, a collaborative end-to-end supply chain for the application of photonics chips, secured €1.1 billion in conditional funding for a six-year initiative. Investments from the Netherlands government and other organizations “will be used to build 200 startups, scale up production, create new applications for photonic chips, and develop infrastructure... » read more

The Race To Much More Advanced Packaging
By Mark LaPedus - 23 Jul, 2020 - Comments: 2

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

The Race To Next-Gen 2.5D/3D Packages
By Mark LaPedus - 23 Sep, 2019 - Comments: 4

Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

What’s Next For DRAM?
By Mark LaPedus - 24 Feb, 2016 - Comments: 2

The DRAM business has always been challenging. Over the years, DRAM suppliers have experienced a number of boom and bust cycles in a competitive landscape. But now, the industry faces a cloudy, if not an uncertain, future. On one front, for example, [getkc id="93" kc_name="DRAM"] vendors face a downturn amid a capacity glut and falling product prices in 2016. But despite the business chal... » read more

An Insider’s Guide To Planar And 3D DRAM
By Mark LaPedus - 18 Feb, 2016 - Comments: 0

Semiconductor Engineering sat down to talk about planar DRAMs, 3D DRAMs, scaling and systems design with Charles Slayman, technical leader of engineering at network equipment giant Cisco Systems. What follows are excerpts of that conversation. SE: What types of DRAM do network equipment OEMs look at or buy these days? Slayman: When we look at DRAM, we look at it for networking applicatio... » read more

Inside The 5G Smartphone
By Mark LaPedus - 20 Aug, 2015 - Comments: 3

Amid a slowdown in the cell phone business, the market is heating up for perhaps the next big thing in wireless—5th generation mobile networks or 5G. In fact, major carriers, chipmakers and telecom equipment vendors are all rushing to get a piece of the action in 5G, which is the follow-on to the current wireless standard known as 4G or long-term evolution (LTE). Intel, Samsung and Qualcom... » read more

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