tag: 3D stacking

Options And Hurdles Come Into Focus For 3D Stacking
By Ed Sperling - 29 May, 2012 - Comments: 0

By Mark LaPedus The initial round of stacked 2.5D and 3D chips based on through-silicon vias (TSVs) has emerged in the market. There are other 2.5D/3D chips in the pipeline, but it’s taking longer than expected to bring these devices into production. There are a range of design, manufacturing, supply chain and cost challenges associated with 2.5D/3D designs. The enormous risk to bring ... » read more

The Next Steps
By Aveek Sarkar - 10 May, 2012 - Comments: 0

By Aveek Sarkar Remaining competitive in today’s semiconductor market means IC designers must meet performance, power and price targets for their design, regardless of the end application. Meeting these mutually conflicting goals requires enlisting the use of several architectural and design techniques, including three-dimensional (3D) or stacked-die architectures that can help meet perfo... » read more

Power Becomes Bigger Issue In Stacked Die
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ed Sperling Concern over getting the heat out of stacked die is well defined, even if the current raft of existing and proposed solutions ranges from ineffective to exotic and expensive. What is less well understood is how to plan for and manage power inside of stacked die. While power and heat frequently go hand in hand—where there is heat there is almost always power dissipation—t... » read more

2.5D Leverages Existing Tools On The Way To 3D
By Ed Sperling - 05 Apr, 2012 - Comments: 0

By Ann Steffora Mutschler As design and manufacturing issues with true 3D design continue to be worked out, interim 2.5D technologies are moving ahead as engineering teams leverage this packaging-driven approach to manage heat, cost, area and yield. Technologies such as Wide I/O memory support 2.5D, and when combined with logic they allow engineering teams to realize a performance increase,... » read more

Reliability Verification For Smart ICs
By Arvind Vel - 05 Apr, 2012 - Comments: 0

By Arvind Shanmugavel The electronic brains behind today’s advanced systems are smart ICs, paving the way for consumer electronics, energy, biomedical, automotive and avionics industries. Power efficiency and system integration are keys to the success of these smart systems. The IC industry has swiftly responded with state-of-the-art low-power techniques and chip integration initiatives f... » read more

Crunch Time
By Ed Sperling - 05 Apr, 2012 - Comments: 0

Never have so many things conspired to make design so difficult—at least not at the same time. At the center of this cornucopia of challenges is power, because more functions and more things now have to fit into a power budget that remains fixed. While some components in a complex SoC may run at lower voltages, you can be assured that others will run hotter and at higher voltages—at leas... » read more

New Winners And Losers
By Ed Sperling - 22 Mar, 2012 - Comments: 0

The realignment of the semiconductor industry has begun, most of it beneath the radar screen. In a disaggregated supply chain, any piece in isolation looks insignificant. But taken together, these shifts begin to paint a picture of a broad realignment and refocusing of the entire industry that ultimately will cement the fortunes of some and create new winners and losers out of others. The fi... » read more

When Stacked Die Make Sense
By Javier DeLaCruz - 21 Mar, 2012 - Comments: 0

By Javier DeLaCruz There are two general flavors of 3D-TSV technology. Images for these can be seen in the previous blog entry The Future of ASICs in 3D. 3D-IC has vias in silicon containing active circuitry. 2.5D is similar, but uses passive silicon, glass or organic interposers to enable very fine pitch interconnection between the active die mounted on top. There is some discussion about ... » read more

3D Standards For The Real World
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Pallab Chatterjee Stacking die has progressed from what is technologically possible to what will be realistically feasible in a fabless or fab-lite world. The big challenges may be less about how to deal with stress caused by a TSV or thermal density and more about companies working together in a disaggregated supply chain. This was quite evident at a recent DesignCon panel dicussion on ... » read more

The Power Of Analog
By Ed Sperling - 01 Dec, 2011 - Comments: 0

The shift into stacked die, expected to begin late next year with a big ramp in 2013, will shine a spotlight on analog design and its effect on power. For years, analog engineers have bragged about just how efficient their portion of a chip was versus digital. We’re about to find out if they’re right. Stacking die will, to a much greater extent, decouple analog from digital and leave it ... » read more

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