7nm Design Success Starts With Multi-Domain Multi-Physics Analysis


Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating volt... » read more

Lower Power Plus Better Performance


The tradeoff between power and performance is becoming less about one versus the other, and more about a dual benefit, as new computing and chip architectures begin rolling out. Neural networking, which is one of the hot buttons for any system that relies on lots of distributed sensors, is essential to get a true picture of what is happening around a car moving down the highway at 65 miles ... » read more

Why Do You Need Chip-Package-System Co-Design And Co-Analysis?


Whether it is the need for sustainable energy, or driving performance while keeping power at bay, or enabling safe and reliable operation of any electronic system, containment of electronic noise — power and signal noise is critical to all of the above. Other factors that impact safe and reliable operation are electromigration (EM), electromagnetic interference (EMI) and mechanical stress ena... » read more

Packaging Wars Begin


The advanced IC-packaging market is turning into a high-stakes competitive battleground, as vendors ramp up the next wave of [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D"] technologies, high-density fan-out packages and others. At one time, the outsourced semiconductor assembly and test ([getkc id="83" comment="OSAT"]) vendors dominated and handled the chip-packaging requirement... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Manufacturing Bits: April 12


Ink FETs The University of Pennsylvania has developed a new way to make chips by using nanocrystal inks. The devices, dubbed nanocrystal field-effect transistors (FETs), could be used one day to develop chips for flexible and wearable applications In the lab, researchers devised spherical nanoscale particles. These particles, which have electrical characteristics, were dispersed in a liquid... » read more

The Week In Review: Manufacturing


South Korea’s SK Hynix led the initial charge in the development of High Bandwidth Memory (HBM), a 3D DRAM technology based on a memory stack and through-silicon vias (TSVs). SK Hynix has been shipping HBM parts in the market. Now, SK Hynix and Samsung are readying the next version of the technology, dubbed High Bandwidth Memory 2 or HMB2, according to a report from The Electronic Times of So... » read more

Memory Choices Grow


Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization. There are plenty of rules ... » read more

Why Packaging Matters


The semiconductor package is changing. What was until very recently considered an afterthought is now becoming a key part of the design process at all major chipmakers, and a critical factor in the extension of Moore's Law. This is a sharp reversal of what was almost universally an afterthought in planar silicon design and manufacturing. Rarely was the package an integral part of the archite... » read more

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