The Next Phase Of Machine Learning


Machine learning is all about doing complex calculations on huge volumes of data with increasing efficiency, and with a growing stockpile of success stories it has rapidly evolved from a rather obscure computer science concept into the go-to method for everything from facial recognition technology to autonomous cars. [getkc id="305" kc_name="Machine learning"] can apply to every corporate fu... » read more

The Case For Combining CPUs With FPGA Fabrics


Given that the industry is beginning to reach the limits of what can physically and economically be achieved through further shrinkage of process geometries, reducing feature size and increasing transistor counts is no longer achieving the same result it once did. Instead the industry is, quite rightly, focusing on fundamentally new system architectures and making better use of available silico... » read more

Tech Talk: eFPGA Programming


Kent Orthner, system architect at Achronix, explains how to program an embedded FPGA and what's different for ASIC engineers. https://youtu.be/uVyflHZi-x8 » read more

eFPGA Acceleration in SoCs


The Speedcore design and integration methodology has been defined with intimate awareness of the difficulties ASIC engineering teams must contend with. All the necessary files and flows for capturing the functional, timing and power characteristics of a user-defined and programmed Speedcore instance, along with support for successfully reconfiguring an already field-deployed Speedcore IP embedd... » read more

The Week In Review: Design


M&A Synopsys acquired Sidense, a provider of antifuse one-time programmable (OTP) non-volatile memory (NVM) for standard-logic CMOS processes. Sidense was founded in 2004 in Canada. Terms of the deal were not disclosed. ArterisIP acquired the software and intellectual property rights of iNoCs, a provider of network-on-chip IP and design tools. Founded in 2007, the Swiss company was spun... » read more

Targeting And Tailoring eFPGAs


Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to discuss what's changing in the embedded FPGA world, why new levels of customization are so important, and difficulty levels for implementing embedded programmability. What follows are excerpts of that discussion. SE: There are numerous ways you can go about creating a chip these days, but many of the prot... » read more

Trimming Waste In Chips


Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

Basics Of Embedded FPGA Acceleration


Making a chip run faster is no longer guaranteed by shrinking features or moving to a different manufacturing process. It now requires a fundamental change in the architecture of the chip itself. The days of the single-processor, or even single multi-core processors, are gone. The focus has shifted to different kinds of processors for different kinds of data and many different protocols and ... » read more

Tech Talk: eFPGA Verification


Chris Pelosi, vice president of hardware engineering at Achronix, explains how to verify an embedded FPGA, and how that compares with verification of discrete FPGAs and ASICs. https://youtu.be/UBLNabLUg9I Related Stories Tech Talk: EFPGA Test How to plan for sufficient coverage for an embedded FPGA and how much it will cost. Embedded FPGAs Going Mainstream? Programmable devices are be... » read more

Evaluating Speedcore IP For Your ASIC


By exploiting Achronix Speedcore embedded FPGA (eFPGA) IP — IP proven in multiple ASIC designs for wireless, datacenter and high-performance computing (HPC) applications — designers of SoCs can now add logic programmability to their solution, resulting in a single ASIC that can adapt to many applications. While many system architects may already have strong ideas on how an eFPGA core could ... » read more

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