tag: advanced packaging

Electromigration Concerns Grow In Advanced Packages
By Laura Peters - 18 Apr, 2024 - Comments: 0

The incessant demand for more speed in chips requires forcing more energy through ever-smaller devices, increasing current density and threatening long-term chip reliability. While this problem is well understood, it's becoming more difficult to contain in leading-edge designs. Of particular concern is electromigration, which is becoming more troublesome in advanced packages with multiple ch... » read more

Powering The Automotive Revolution: Advanced Packaging For Next-Generation Vehicle Computing
By Prasad Dhond - 18 Apr, 2024 - Comments: 0

Automotive processors are rapidly adopting advanced process nodes. NXP announced the development of 5 nm automotive processors in 2020 [1], Mobileye announced EyeQ Ultra using 5 nm technology during CES 2022 [2], and TSMC announced its “Auto Early” 3 nm processes in 2023 [3]. In the past, the automotive industry was slow to adopt the latest semiconductor technologies due to reliability conc... » read more

Advanced Packaging Design For Heterogeneous Integration
By CP Hung - 18 Apr, 2024 - Comments: 0

As device scaling slows down, a key system functional integration technology is emerging: heterogeneous integration (HI). It leverages advanced packaging technology to achieve higher functional density and lower cost per function. With the continuous development of major semiconductor applications such as AI HPC, edge AI and autonomous electrical vehicles, traditional chips are transforming i... » read more

The Challenges Of Working With Photonics
By Karen Heyman - 01 Apr, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about where photonics is most useful — and most vulnerable — with James Pond, fellow at Ansys; Gilles Lamant, distinguished engineer at Cadence; and Mitch Heins, business development manager for photonic solutions at Synopsys. What follows are excerpts of that conversation. To view part one of this discussion, click here. ... » read more

What’s Missing In 2.5D EDA Tools
By Brian Bailey - 28 Mar, 2024 - Comments: 0

Gaps in EDA tool chains for 2.5D designs are limiting the adoption of this advanced packaging approach, which so far has been largely confined to high-performance computing. But as the rest of the chip industry begins migrating toward advanced packaging and chiplets, the EDA industry is starting to change direction. There are learning periods with all new technologies, and 2.5D advanced pack... » read more

3D-IC Intensifies Demand For Multi-Physics Simulation
By Ann Mutschler - 20 Mar, 2024 - Comments: 0

The introduction of full 3D-ICs will require a simultaneous analysis of various physical effects under different workloads, a step-function change that will add complexity at every step of the design flow, expand and alter job responsibilities, and bring together the analog and digital design worlds in unprecedented ways. 3D-ICs will be the highest-performance advanced packaging option, in s... » read more

The Rising Price Of Power In Chips
By Ed Sperling - 14 Mar, 2024 - Comments: 0

Power is everything when it comes to processing and storing data, and much of it isn't good. Power-related issues, particularly heat, dominate chip and system designs today, and those issues are widening and multiplying. Transistor density has reached a point where these tiny digital switches are generating more heat than can be removed through traditional means. That may sound manageable e... » read more

How Multiphysics Simulation Enables 3D-IC Implementation At The Speed Of Light
By Ansys - 13 Mar, 2024 - Comments: 0

Electronic designers need greater integration densities and faster data transfer rates to meet the increased performance requirements of technologies like 5G/6G, autonomous driving, and artificial intelligence. The semiconductor industry is shifting toward 3D-IC design to keep up with the ever-growing demand for high-performance and power-efficient devices that has outpaced the capabilities o... » read more

UCIe-3D: SiP Architectures With Advanced 3D Packaging With Shrinking Bump Pitches (Intel)
By Technical Paper Link - 12 Mar, 2024 - Comments: 0

A technical paper titled “High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express” was published by researchers at Intel. Abstract: "Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0... » read more

New Issues In Power Semiconductors
By Ed Sperling - 26 Feb, 2024 - Comments: 0

The number of challenges is growing in power semiconductors, just as it is in traditional chips. Thermal dissipation and gradients, new design rules, and layout issues need to be considered, especially in the context of higher voltage and increased performance demands. Roland Jancke, design methodology head in Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about issues in int... » read more

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