Optimizing Multiple IoT Layers


As the number of connected devices rises, so do questions about how to optimize them for target markets, how to ensure they play nicely together, and how to bring them to market quickly and inexpensively. [getkc id="76" kc_name="IoT"] is broad term that encompasses a lot of disparate pieces for devices, systems, and connected systems. At the highest levels are hardware and software, but with... » read more

Advanced Packaging Requires Better Yield


Whether Moore's Laws truly ends, or whether the semiconductor industry reaches into the Angstrom world after 3nm—the semiconductor industry dislikes fractions—advanced packaging increasingly will dominate semiconductor designs. Apple already is on board with its iPhone 7, using TSMC's fan-out approach. And all of the major foundries and OSATs are lining up with a long list of capabilitie... » read more

Making 2.5D, Fan-Outs Cheaper


Now that it has been shown to work, the race is on to make advanced [getkc id="27" kc_name="packaging"] more affordable. While device scaling could continue for another decade or more, the number of companies that can afford to develop SoCs at the leading edge will continue to decline. The question now being addressed is what can supplant it, supplement it, or redefine it. At the center o... » read more

Overcoming The Limits Of Scaling


Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

2.5D Surprises And Alternatives


Semiconductor Engineering sat to discuss advanced packaging issues with Juan Rey, senior director of engineering for Calibre at [getentity id="22017" e_name="Mentor Graphics"]; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; and Lisa Minwell, [getentity id="22242" e_name="eSilicon's"] senior director of IP marketing. What follows are excerpts of that conversation. ... » read more

Lower Power Plus Better Performance


The tradeoff between power and performance is becoming less about one versus the other, and more about a dual benefit, as new computing and chip architectures begin rolling out. Neural networking, which is one of the hot buttons for any system that relies on lots of distributed sensors, is essential to get a true picture of what is happening around a car moving down the highway at 65 miles ... » read more

Packaging Wars Begin


The advanced IC-packaging market is turning into a high-stakes competitive battleground, as vendors ramp up the next wave of [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D"] technologies, high-density fan-out packages and others. At one time, the outsourced semiconductor assembly and test ([getkc id="83" comment="OSAT"]) vendors dominated and handled the chip-packaging requirement... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Power Options And Issues


In the quest to get SoC power right as early as possible in the design flow, it still holds true that the biggest impact occurs at the beginning of the project, with diminished results as a design progresses through the flow toward tapeout. [getentity id="22186" e_name="ARM's"] big.LITTLE architecture has gained a lot of traction here, prompting MediaTek to introduce its Tri-Gear big.Medium.... » read more

Stepping Back From Scaling


Architectures, packaging and software are becoming core areas for semiconductor research and development, setting the stage for a series of shifts that will impact a large swath of the semiconductor industry. While there is still demand from the largest chipmakers for increased density at the next process node, the underlying economics for foundries, equipment vendors and IP developers are f... » read more

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