Chip Industry Week In Review

By The SE Staff - 19 Apr, 2024 - Comments: 0

SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

Chip Industry Week In Review

By The SE Staff - 12 Apr, 2024 - Comments: 0

Applied Materials may scale back or cancel its $4 billion new Silicon Valley R&D facility in light of the U.S. government's recent announcement to reduce funding for construction, modernization, or expansion of semiconductor research and development (R&D) facilities in the United States, according to the San Francisco Chronicle. TSMC could receive up to $6.6 billion in direct funding... » read more

IC Test And Quality Requirements Drive New Collaboration

By Laura Peters - 09 Apr, 2024 - Comments: 0

Rapidly increasing chip and package complexity, coupled with an incessant demand for more reliability, has triggered a frenzy of alliances and working relationships that are starting to redefine how chips are tested and monitored. At the core of this shift is a growing recognition that no company can do everything, and that to work together will require much tighter integration of flows, met... » read more

New Strategies For Interpreting Data Variability

By Gregory Haley - 09 Apr, 2024 - Comments: 0

Every measurement counts at the nanoscopic scale of modern semiconductor processes, but with each new process node the number of measurements and the need for accuracy escalate dramatically. Petabytes of new data are being generated and used in every aspect of the manufacturing process for informed decision-making, process optimization, and the continuous pursuit of quality and yield. Most f... » read more

Fabrication Of Vertical-Taper Structures For Silicon Photonic Devices By Using Local-Thickness-Thinning Process

By Advantest - 09 Apr, 2024 - Comments: 0

Authors: Shunsuke Abe, Hideo Hara, Shin Masuda, and Hirohito Yamada. This paper describes a simple fabrication process of verticaltaper structures which can locally tune the thickness of silicon photonic devices. For low-loss spot-size conversion, taper angles less than 10° are required. To fabricate the gradual-slope shape of the vertical tapers, we have developed a step-andexposure lithog... » read more

DTCO/STCO Create Path For Faster Yield Ramps

By Laura Peters - 12 Mar, 2024 - Comments: 0

Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

AI/ML Challenges In Test and Metrology

By Gregory Haley - 12 Mar, 2024 - Comments: 0

The integration of artificial intelligence and machine learning (AI/ML) into semiconductor test and metrology is redefining the landscape for chip fabrication, which will be essential at advanced nodes and in increasingly dense advanced packages. Fabs today are inundated by vast amounts of data collected across multiple manufacturing processes, and AI/ML solutions are viewed as essential for... » read more

Strategies For Detecting Sources Of Silent Data Corruption

By Anne Meixner - 12 Mar, 2024 - Comments: 0

Engineering teams are wrestling with how to identify the root causes of silent data corruption (SDC) in a timely and cost-effective way, but the solutions are turning out to be broader and more complex than simply fixing a single defect. This is particularly vexing for data center reliability, accessibility and serviceability (RAS) engineering teams, because even the best tools and methodolo... » read more

Blog Review: Feb. 14

By Liz Allan - 14 Feb, 2024 - Comments: 0

Siemens’ Dilan Heredia and Karen Chow explain why fast, accurate parasitic extraction (PEX) is essential to design success, especially for the 3 nm node and GAAFETs. Synopsys’ Srinivas Velivala debunks the myth that layout-versus-schematic (LVS) checking is a static step in the chip development process, and details its evolving role in modern SoCs. Cadence’s Mark Seymour digs into a... » read more

Adaptive Test Ramps For Data Intelligence Era

By Laura Peters - 08 Feb, 2024 - Comments: 0

Widely available and nearly unlimited compute resources, coupled with the availability of sophisticated algorithms, are opening the door to adaptive testing. But the speed at which this testing approach is adopted will continue to vary due to persistent concerns about data sharing and the potential for IP theft and data leakage. Adaptive testing is all about making timely changes to a test p... » read more

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Chip Industry Week In Review

Chip Industry Week In Review

IC Test And Quality Requirements Drive New Collaboration

New Strategies For Interpreting Data Variability

Fabrication Of Vertical-Taper Structures For Silicon Photonic Devices By Using Local-Thickness-Thinning Process

DTCO/STCO Create Path For Faster Yield Ramps

AI/ML Challenges In Test and Metrology

Strategies For Detecting Sources Of Silent Data Corruption

Blog Review: Feb. 14

Adaptive Test Ramps For Data Intelligence Era

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