Interconnect Challenges Rising


Chipmakers are ramping up their 14nm finFET processes, with 10nm and 7nm slated to ship possibly later this year or next. At 10nm and beyond, IC vendors are determined to scale the two main parts of the [getkc id="185" kc_name="finFET"] structure—the transistor and interconnects. Generally, transistor scaling will remain challenging at advanced nodes. And on top of that, the interconnects ... » read more

The Deep And Dark Webs


From time to time we hear a snippet or two about the “other” Web – the dark side of the Internet and the Web. For the most part, until something happens that brings the activity within that arena to the surface (such as the recent Silk Road exposure where anything was available for a price), that segment quietly hums along. But that is about to change. Once the IoE evolution gets tract... » read more

How Long Will FinFETs Last?


Semiconductor Engineering sat down to discuss how long FinFETs will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at [getentity id="22032" e_name="Cadence"]; Juan Rey, Sr. Director of Engineering for Calibre R&D at [getentity id="22017" e_name="Mentor Graphics"]; Kelvin Low, Senior Director Foundry Marketing at [getentity id="22865" e_name="Samsung"]; and Vic... » read more

Data Centers At Risk


Large companies have been utilizing private clouds for the past half-decade as a way to safeguard their data and still take advantage of outsourcing economics. Using that approach, the data center has become an in-house service provider with its own P&L, which is why there has been such a push to improve efficiency well beyond the server consolidation that was made possible with virtualization.... » read more

Interconnect Challenges Grow


Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost. Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within ... » read more

Experts At The Table: Process Technology Challenges


By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, v... » read more