The Week In Review: Design


M&A Synapse Design acquired Asilicon, a design services firm based in Ranchi Jharkhand, India. Through the acquisition, Synapse Design adds a second design center in India and gains an additional 80 engineers. "The focus of the Ranchi office will be to provide lower-cost offshore design center services for our customer's designs targeting 7- and 10-nm process technology," said Satish Bag... » read more

Blog Review: April 5


In a video, Cadence's Megha Daga digs into the different architectural layers present in convolutional neural networks and how they contribute to object detection and classification in a real world scenario. Mentor's Mike Santarini argues that as things become increasingly connected, the stakes of bad design and bad verification are higher than they've ever been. Synopsys' Robert Vamosi w... » read more

Custom Chip Verification Issues Grow


With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom. As a result, electronic systems for applications such as mobile, consumer, and automotive increasingly are becoming more difficult to design due to the exacting performance requirements of these applications. This is particularly evident in custom design, including... » read more

Leveraging The Power Of VDMA Engines For Computer Vision Apps


It's pretty hard to overestimate the role of heterogeneous embedded systems based on Xilinx Zynq-7000 All-Programmable devices in tasks like computer vision. Many consumer electronics and specialized devices are emerging to facilitate and improve industries such as medical, automotive, security, and IoT. The combination of high-performance ARM application processing and Xilinx programmable F... » read more

Challenges Grow For IP Reuse


As chip complexity increases, so does the complexity of IP blocks being developed for those designs. That is making it much more difficult to re-use IP from one design to the next, or even to integrate new IP into an SoC. What is changing is the perception that standard [getkc id="43" kc_name="IP"] works the same in every design. Moreover, well-developed [getkc id="100" kc_name="methodologie... » read more

Quality Issues Widen


As the amount of semiconductor content in cars, medical and industrial applications increases, so does the concern about how long these devices will function properly—and what exactly that means. Quality is frequently a fuzzy concept. In mobile phones, problems have ranged from bad antenna placement, which resulted in batteries draining too quickly, to features that take too long to load. ... » read more

The Week In Review: Design


Legal Synopsys filed suit against Ubiquiti Networks and its project leader for "circumventing technological measures that effectively control access to Synopsys' software." The suit, filed in U.S. District Court in San Jose, claims that Ubiquiti used counterfeit keys obtained or created with tools from hacker websites to circumvent Synopsys' License Key system. Ubiquiti, based in San Jose, d... » read more

Better Code With RTL Linting And CDC Verification


Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

The Week In Review: Design


Tools Mentor Graphics launched the company's third generation data-center friendly emulation platform, Veloce Strato. The emulator has a capacity of 2.5BG when fully loaded, and total capacity can be increased by linking emulators. It has available slots for 64 Advanced Verification Boards (AVBs) and fully loaded consumes up to 50KW (22.7 W/Mgate) of power. Aldec uncorked the latest versi... » read more

The Week In Review: Design


Tools Synopsys announced the latest version of its VCS functional verification solution, which integrates native fine-grained parallelism (FGP) and additional engine optimizations for simulation on existing x86 CPU server configurations. Aldec released the latest version of its requirements lifecycle management solutions for FPGAs/SoCs, adding certification document templates and review c... » read more

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