Startup Funding: April 2023


Packaging was a hot spot in April, with one of the largest rounds going to a middle-end-of-line advanced packaging company. A second packaging company also drew significant funding for its focus on wafer-level packaging for CMOS image sensors. Two packaging substrate manufacturers also saw investment. Two photoresist makers also drew sizeable rounds. Both they and the packaging companies are... » read more

Startup Funding: December 2022


The month of December saw six rounds of $100 million or more. The largest, at a massive half-billion dollars, will support manufacturing of 12-inch monocrystalline silicon polished wafers and epitaxial wafers in China. The company is aiming for a production rate of 1 million pieces a month when current expansion is completed. Also in the half-billion club last month is a company making auton... » read more

Week In Review: Design, Low Power


Tools, design, chips Altair, a provider of software and cloud services for CAE, HPC, simulation, and data analysis, acquired Concept Engineering, a provider of automatic schematic generation tools, electronic circuit and wire harness visualization platforms that provide on-the-fly visual rendering, and electronic design debug solutions. “Concept Engineering’s advanced, reactive visualizati... » read more

Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Using More Verification Cores


Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Do Parallel Tools Make Sense?


Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Why Parallelization Is So Hard


Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

The Week In Review: Design


M&A Altair acquired Runtime Design Automation. Founded in 1995, Runtime provides tools for optimizing usage of EDA tools, including flow management, job scheduling, and license utilization, as well as tools for optimizing HPC network resources. Altair's focus is on engineering simulation, with tools for HPC resource management and IoT data analytics. Terms of the deal were not disclosed. ... » read more

The Week In Review: IoT


Analysis The Internet of Things may be entering the infamous “Trough of Disillusionment” in the Gartner Hype Cycle, according to some observers. “There’s a general malaise growing around IoT. Where is this shiny, artificially intelligent, fully connected future of things we were promised?” iobeam CEO Ajay Kulkarni writes in this analysis. Others are more sanguine about the IoT. Clear... » read more

The Week In Review: Manufacturing


Qualcomm recently announced the new Snapdragon 820. The cell-phone chipset is based on Samsung Electronics’ new 14nm LPP (Low-Power Plus) process, the second-generation of the company’s 14nm finFET process technology. What’s next? Qualcomm is developing the Snapdragon 830. “Snapdragon 830 leaks indicate that the chip will sport 8GB of RAM, an enhanced Kryo custom architecture, and fabbe... » read more

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