How To Speed Signoff Extraction By 5X With Next-Generation Extraction Tool

Parasitic extraction, particularly in the digital world, is becoming an increasingly time-consuming process. Not surprising, considering the explosion in interconnect corners, increasing design sizes and number of parasitics, and complex modeling features at advanced nodes, including FinFETs. This paper discusses capabilities you should have in order to overcome parasitic extraction challenges,... » read more

The Week In Review: Design

Tools Synopsys rolled out a major new release of its place and route tool, the centerpiece of its physical design platform, offering up to 10X improvement in speed—a combination of 5X faster implementation and 2X larger capacity. Co-CEO Aart de Geus called it the most significant product in the company’s history. Synopsys also rolled out an AMS verification platform to accelerate regres... » read more

Mentor Buys Berkeley Design

Mentor Graphics announced today that it has acquired Berkeley Design Automation, staking a claim on the expanding market for analog, mixed-signal and RF verification. The deal puts Mentor on firm footing against Synopsys and Cadence, just as the opportunity for the Internet of Things (IoT), including automotive and medical design, begins to show real promise. Until this move, Mentor has larg... » read more

Experts At The Table: The Future Of Verification

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Cost vs. Value

By Ann Steffora Mutschler The increasing amount of mixed-signal content being included in SoCs for automotive, networking and all manner of mobile devices is reinvigorating the mixed-signal industry. While this is great news for companies playing in anything related to mixed-signal technology, it also means increasing complexity for the engineering teams pulling all the pieces together. “... » read more

Reducing Circuitry To Reduce Power

By Ann Steffora Mutschler Power is at the top of the list of concerns for design teams today. Consequently, engineers are constantly looking at new techniques and architectural approaches to lower and management the power and energy consumption of their devices. This has resulted in some incredible engineering feats, turning parts of a device on and off as needed, applying different volta... » read more

AMS Challenges Growing

By David Lammers Analog and mixed signal (MS) devices will play an ever-increasing role in saving energy, particularly as the “Internet of Things” expands to about 10 billion units per year over the next decade. But as leading-edge design rules scale to 28nm and below, enhanced with high-k/metal gate technologies, it is becoming increasingly challenging to integrate AMS devices on SoCs. ... » read more

AMS Reference Flow 1.0: Ready For Prime Time?

By Pallab Chatterjee TSMC recently announced a game-changing flow for 32nm/28nm Analog Mixed Signal (AMS) design. The AMS flow 1.0 includes tools from multiple vendors that are sequenced to take a design from concept and device creation all the way to release to being included as IP in an SoC. The flow that is being offered is a departure from traditional custom analog and custom AMS design. ... » read more