The Week In Review: Design


M&A ARM made two acquisitions to add the new NarrowBand-IoT (NB-IoT) low power wide area connectivity standard to its designs: Mistbase, founded in 2015 in Sweden, provides a complete NB-IoT physical layer implementation solution, while London-based NextG-Com, founded in 2008, offers a complete layer two and three software stack for NB-IoT. Tools Synopsys released the latest versio... » read more

Blog Review: Feb. 15


Mentor's Jean-Marie Brunet looks at factors driving the growth of hardware emulation for SoCs. Cadence's Dave Pursley asserts that the role of hardware developers is about to change for the better. Synopsys' Robert Vamosi says that major software vulnerabilities are becoming less frequent, in spite of hype surrounding named bugs. ARM's Rhonda Dirvin discusses the release of the OpenFog... » read more

Test More Complex For Cars, IoT


With increasing focus on safety-critical semiconductors—driven by ADAS, IoT, and security—functional safety concerns are going through the roof. Engineering teams are scrambling to determine how to conduct better in-field or online testing because test no longer can be an afterthought. This has been a common theme across the automotive ecosystem for the past few years, and as the automot... » read more

Confidence In 7nm Designs Requires Multi-Variable, Multi-Scenario Analysis


As designs move toward 7-nanometer (nm) process nodes, engineering and production cost dramatically increases and the stake in getting the design right the first time becomes significantly higher than ever before. You are faced with the question, “how confident are you in your design analysis coverage?” Tighter noise margin, increasing power density, faster switching current and greater ... » read more

What Can Be Cut From A Design?


A long-standing approach of throwing everything into a chip increasingly is being replaced by a focus on what can be left out it. This shift is happening at every level, from the initial design to implementation. After years of trying to fill every square nanometer of real estate on a piece of silicon with memory and logic, doubling the number of [getkc id="26" kc_name="transistors"] from on... » read more

Electrothermal Mechanical Stress Reference Design Flow For Printed Circuit Boards And Electronic Packages


This paper presents a reference design flow for solving the electrical, thermal and mechanical challenges of a printed circuit board (PCB) using simulation tools from ANSYS. This approach can be utilized for all electrical CAD (ECAD) types such as IC packages, touch panel displays, and glass and silicon interposers. The authors followed this reference design flow for analyzing a PCB virtual pro... » read more

Blog Review: Feb. 8


Mentor's Craig Armenti looks at some of the challenges involved with multi-board PCB or system design. Cadence's Paul McLellan highlights a presentation by Igor Keller on the state of the art in static timing analysis. Synopsys' Eric Huang has some ideas for USB interoperability testing. Intel's Ron Wilson delves into the current state of 5G, and why perspectives on that differ. Ans... » read more

Chip-Package-Board Issues Grow


As systems migrate from a single die in a single package on a board, to multiple dies with multiple packaging options and multiple PCB form factors, it is becoming critical to move system planning, assembly, and optimization much earlier in the design-through-manufacturing flow. This is easier said than done. Multiple tools and operating systems are now used at each phase of the flow, partic... » read more

Betting On Wafer-Level Fan-Outs


Advanced packaging is starting to gain traction as a commercially viable business model rather than just one more possible option, propelled by the technical difficulties in routing signals at 10nm and 7nm and skyrocketing costs of device scaling on a single die. The inclusion of a [getkc id="202" kc_name="fan-out"] package for logic in Apple's iPhone 7, based on TSMC's Integrated Fan-Out (... » read more

The Week In Review: Design


Tools Synopsys announced the latest version of its VCS functional verification solution, which integrates native fine-grained parallelism (FGP) and additional engine optimizations for simulation on existing x86 CPU server configurations. Aldec released the latest version of its requirements lifecycle management solutions for FPGAs/SoCs, adding certification document templates and review c... » read more

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