Tech Talk: 7nm Power


Annapoorna Krishnaswamy, lead applications engineer at ANSYS, talks with Semiconductor Engineering about power-related changes at 7nm and what engineering teams need to watch out for as they move down to the latest process technology. https://youtu.be/Ym46ssJPeHM » read more

Shrink Or Package?


Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

Modeling On-Chip Variation At 10/7nm


Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die. At simulation's root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. ... » read more

Blog Review: June 14


In a video, Cadence's Tom Hackett looks at the evolving von Neumann computer architecture and the development of CCIX driven by recent cloud computing challenges. Mentor's Puneet Sinha notes it's been 17 years since the Toyota Prius went on sale worldwide, and looks ahead to the next 17 years of electric vehicles. Synopsys' Sri Deepti Pisipati gives an overview of the different topologies... » read more

The Week In Review: Design


Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

Transient Power Problems Rising


Transient power is becoming much more problematic at 10/7nm, adding yet another level of complexity for design teams already wrestling with power issues caused by leakage, a variety of power management techniques to control dynamic power, and leakage current. At each new node there is less headroom for engineering teams to address these problems, and more likelihood that what they do in one ... » read more

Simulation-Driven Product Development In Additive Manufacturing


Additive manufacturing, or 3-D printing, has the potential to radically change the way in which products are conceived and designed. The additive process allows for unprecedented design complexity and design freedoms. Full subassemblies can be produced in one print eliminating costly joining operations. Parts can be customized and produced in small, made- to-order batches. Parts can be produced... » read more

The Week In Review: Design


Tools Startup Austemper Design unveiled a functional safety tool suite that includes safety analysis that applies default values from industry standards ISO26262 and/or IEC61508 for Failures-in-Time (FIT) rates, tools to handle safety synthesis and augment design structures, and a parallel fault simulator with hybrid simulation capabilities. SystemVerilog and VHDL parsers from Verific serve ... » read more

The Week In Review: Design


M&A Consultancy Sondrel acquired IMGworks, formerly the design services unit of Imagination. Sondrel says it plans to focus on design services for ADAS systems, AI, and machine vision and learning devices. Terms of the deal were not disclosed. Tools Cadence expanded its formal verification platform, JasperGold, adding linting and clock domain crossing apps that address RTL signoff ... » read more

Maintaining Power Profiles At 10/7nm


Understanding power consumption in detail is now a must-have of electronic design at 10nm and below, putting more pressure on SoC verification to ensure a device not only works, but meets the power budget. As part of this, the complete system must be run in a realistic manner — at the system-level — when the design and verification teams are looking at the effects of power during hardwar... » read more

← Older posts