tag: ASIC design

Better Choreography Required For Complex Chips
By Karen Heyman - 22 Jun, 2023 - Comments: 0

The rapidly growing number of features and options in chip design are forcing engineering teams to ratchet up their planning around who does what, when it gets done, and how various components will interact. In effect, more elements in the design flow need to be choreographed much more precisely. Some steps have to shift further left, while others need to be considered earlier in the plannin... » read more

RTL Architect: Simply Better RTL
By Synopsys - 27 May, 2020 - Comments: 0

Electronic devices play a key role in society. They connect us to one another through voice, video and chat. They entertain, educate, protect and heal us in new and ever-expanding ways. They have changed the way we work, live and play. Silicon chips are the fast beating heart (2 to 3 billion beats per second) of these devices. For decades, the relentless advancements in semiconductor process te... » read more

Accelerating Toshiba’s Advanced System-on-Chip (SoC) Design with Synopsys’ Fusion Compiler
By Synopsys - 23 Oct, 2019 - Comments: 0

Authors: Mitchy M. Mitsuyasu, Senior Specialist, Semiconductor R&D, Toshiba Electronic Device & Storage Corp.; Akira Nikaido, Director Product Marketing, Synopsys. Toshiba Electronic Devices & Storage Corporation, part of the broader Toshiba, Kawasaki Japan, has long been a technology leader in Advanced SoCs spanning multiple, key market verticals. This includes automotive, communications, I... » read more

SEM Analysis Reveals Real Cause Of Chip Failure
By DELTA, a part of FORCE Technology - 08 Jul, 2019 - Comments: 0

When it comes to ASIC design, DELTA’s motto is “first time right”. When the first wafers from the wafer fab showed severe electrical malfunction, we were extremely frustrated. To investigate the failure, the design team started electrical characterization of prototypes. Overall, a short between power and ground was observed and furthermore RF inputs exhibited strange VI characteristics. T... » read more

Clock Domain Crossings in the FPGA World
By Aldec - 30 Jan, 2019 - Comments: 0

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More import... » read more

Advanced SoC Interconnect IP
By Kurt Shuler - 28 Feb, 2013 - Comments: 0

By Kurt Shuler I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year. But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward. The one lesson learned is that flexibility for SoC designs is increasingly more important. In ... » read more

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