tag: ATPG

AI-Driven Test Optimization Solves Semiconductor Test Costs And Design Schedules
By Sri Ganta - 08 Feb, 2024 - Comments: 0

Artificial Intelligence has become a pervasive technology that is being applied to solve today’s complex problems, especially in the areas involving exponentially large amounts of data, their analysis, and corresponding decision making that are otherwise limited by human abilities. Therefore, complex challenges in semiconductor design, test and manufacturing are a perfect match for AI. The... » read more

Testing ICs Faster, Sooner, And Better
By Laura Peters - 12 Dec, 2023 - Comments: 0

The infrastructure around semiconductor testing is changing as companies build systems capable of managing big data, utilizing real-time data streams and analysis to reduce escape rates on complex IC devices. At the heart of these tooling and operational changes is the need to solve infant mortality issues faster, and to catch latent failures before they become reliability problems in the fi... » read more

New Type Of Hardware Trojans Based On Logic Locking
By Technical Paper Link - 03 Oct, 2023 - Comments: 0

A technical paper titled “Logic Locking based Trojans: A Friend Turns Foe” was published by researchers at University of Maryland and University of Florida. Abstract: "Logic locking and hardware Trojans are two fields in hardware security that have been mostly developed independently from each other. In this paper, we identify the relationship between these two fields. We find that a com... » read more

Reducing Chip Test Costs With AI-Based Pattern Optimization
By Rahul Singhal - 31 Jul, 2023 - Comments: 0

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested. The slower the test throughput, the more automatic test equipment (ATE) is needed to meet production throughput demands. This is a huge issue for chip producers, since high pin counts, blazingly ... » read more

Journey From Cell-Aware To Device-Aware Testing Begins
By Laura Peters - 06 Jun, 2023 - Comments: 0

Early results of using device-aware testing on alternative memories show expanded test coverage, but this is just the start. Once the semiconductor industry realized that it was suffering from device failures even when test programs achieved 100% fault coverage, it went about addressing this disconnect between the way defects manifest themselves inside devices and the commonly used fault mod... » read more

Pinpointing Timing Delays Can Improve Chip Reliability
By Anne Meixner - 09 May, 2023 - Comments: 0

Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

What Data Center Chipmakers Can Learn From Automotive
By Anne Meixner - 11 Apr, 2023 - Comments: 2

Automotive OEMs are demanding their semiconductor suppliers achieve a nearly unmeasurable target of 10 defective parts per billion (DPPB). Whether this is realistic remains to be seen, but systems companies are looking to emulate that level of quality for their data center SoCs. Building to that quality level is more expensive up front, although ultimately it can save costs versus having to ... » read more

Power-Aware Test: Beyond Low-Power Test
By Rahul Singhal - 11 Apr, 2023 - Comments: 0

By Rahul Singhal and Likith Kumar Manchukonda Power consumption is one of the key considerations when designing today’s semiconductor chips and systems. Over the years, the constant need for higher performance and more functions from the chips has been driving the continuous requirement for higher transistor density. The process node scaling makes this possible by reducing transistor sizes... » read more

Testability Analysis Based On Ever-Evolving Technology
By Pawini Mahajan - 06 Dec, 2022 - Comments: 0

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by high gate counts and an array of internally developed and third-party IP integrated into their designs. Understanding if one can create high-quality manufacturing tests for these complex designs mus... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows
By Ann Mutschler - 28 Nov, 2022 - Comments: 0

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

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