The Week In Review: Design


Tools Startup Austemper Design unveiled a functional safety tool suite that includes safety analysis that applies default values from industry standards ISO26262 and/or IEC61508 for Failures-in-Time (FIT) rates, tools to handle safety synthesis and augment design structures, and a parallel fault simulator with hybrid simulation capabilities. SystemVerilog and VHDL parsers from Verific serve ... » read more

Preparations for DAC


The 53rd DAC is just days away now and the program is pretty well established at this point. It is returning to Austin after a couple of years in San Francisco. In 2013 it was held in this location for the first time and there was a herculean effort to bring the local design community to the event. They did amazing well and while attendance fell slightly compared to the previous year in San Die... » read more