What’s Important For IoT—Power, Performance Or Integration?


Semiconductor Engineering sat down with Steve Hardin, director of product development for AT&T's IoT Solutions Group; Wayne Dai, CEO of VeriSilicon; John Koeter, vice president of the Solutions Group at [getentity id="22035" e_name="Synopsys"]; and Rajeev Rajan, vice president for IoT at [getentity id="22819" comment="GlobalFoundries"]. What follows are excerpts of that conversation. To vie... » read more

Reaching The Power Budget


Everything related to power in chip design today is a big deal—and it’s just getting bigger. Meeting the power budget is becoming harder at each new node, but it's also becoming difficult in a number of new application areas at existing nodes. That's a big problem because [getkc id="108" kc_name="power"] is now considered a competitive advantage in many markets. It's also one of the most... » read more

What’s Important For IoT—Power, Performance Or Integration?


Semiconductor Engineering sat down with Steve Hardin, director of product development for AT&T's IoT Solutions Group; Wayne Dai, CEO of VeriSilicon; John Koeter, vice president of the Solutions Group at [getentity id="22035" e_name="Synopsys"]; and Rajeev Rajan, vice president for IoT at [getentity id="22819" comment="GlobalFoundries"]. What follows are excerpts of that conversation. SE:... » read more

Building Faster Chips


By Ed Sperling and Jeff Dorsch An explosion in IoT sensor data, the onset of deep learning and AI, and the commercial rollout of augmented and virtual reality are driving a renewed interest in performance as the key metric for semiconductor design. Throughout the past decade in which mobility/smartphone dominated chip design, power replaced performance as the top driver. Processors ha... » read more

Moore’s Law Reset?


GlobalFoundries today took the wraps off its 22nm FD-SOI process, promising to extend Moore's Law technologically without altering the economic equation—at least for the next couple of process nodes. Subramani Kengeri, vice president of global design solutions at [getentity id="22819" comment="GlobalFoundries"], said 22nm FD-SOI will provide the same 30% improvement in PPA that has been c... » read more

Designing For Energy Efficiency


Swiss watchmakers have nothing to worry about for the moment. As top-name companies crowd into the wearable market with full-featured watches, limits on battery life and frequent charges undoubtedly will limit their popularity. Smart watches look cool or clunky, depending upon your perspective, but none of them lasts long enough between charges to be a serious market contender. That's certai... » read more

ARM Cortex-A53, UPF & FD-SOI


The IEEE Standards Association Symposium on Electronic Design Automation (EDA) Interoperability was held on Oct. 24. I found the first session, Interoperability Challenges: Power Management in Silicon, with presentations by Erich Marschner of Mentor Graphics and Stuart Riches and Adnan Khan (both from ARM) to be particularly interesting. Earlier this year, the IEEE announced a new version of UP... » read more

Pushing The Limits


Ever since the turn of the millennium, researchers have been warning that wires and interconnects will have issues. Electron crashes were reported as early as 2001, and electromigration is rising to the forefront of problems at advanced nodes. The result? Chipmakers are looking at thicker wires for the first time as a way of dealing with resistance and capacitance issues. While this makes se... » read more

New Issues In Signoff


By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more