tag: body biasing

Forward Body Biasing in Bulk Cryo-CMOS With Negligible Leakage (TU Delft)
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Cryogenic-Aware Forward Body Biasing in Bulk CMOS" was published by researchers at QuTech, Tu Delft. Abstract "Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in bulk CMOS is proposed, which can operate up to the nominal supply without prob... » read more

Blog Review: Oct. 24
By Jesse Allen - 24 Oct, 2018 - Comments: 0

Arm's Shidhartha Das digs into Power Delivery Networks with a look at how the specific roles of different components work to provide smooth supply conditions. In a video, VLSI Research's Dan Hutcheson chats with D2S CEO Aki Fujimura about the state of the photomask market, EUV optimism, and the most interesting findings from this year's eBeam Initiative survey. Synopsys' Prasad Subudhi K.... » read more

22nm Process Technology
By Ed Sperling - 19 Jul, 2018 - Comments: 0

Jamie Shaeffer, senior director of product line management at GlobalFoundries, talks about how FD-SOI compares with bulk technologies, where it will be used and why, and future stacking options. https://youtu.be/2i7GJRxcNRs » read more

Chipmakers Look Beyond Scaling
By Ed Sperling - 17 May, 2018 - Comments: 1

Gary Patton, CTO of GlobalFoundries, sat down with Semiconductor Engineering to discuss the rollout of EUV, the rising cost of designing chips at the most advanced nodes, and the growing popularity of 22nm planar FD-SOI in a number of markets. What follows are excerpts of that conversation. SE: You've just begun deploying EUV. Are you experiencing any issues? Patton: It's a very complicat... » read more

IP And Power
By Brian Bailey - 08 Mar, 2018 - Comments: 0

[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

FD-SOI Adoption Expands
By Ed Sperling - 21 Feb, 2018 - Comments: 2

Fully depleted silicon-on-insulator (FD-SOI) is gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs. For years, [getkc id="220" kc_name="FD-SOI"] has been viewed as an either/or solution targeted at the same markets as bulk [gettech id="31093" c... » read more

Body Biasing For Analog Design
By Fraunhofer IIS/EAS - 13 Dec, 2017 - Comments: 0

This paper presents the practical application of body biasing control of ultra-deep submicron FD-SOI technologies for analog and mixed-signal designs. The body biasing control is dedicated for dynamic control of the trade- off between speed vs. power consumption for advanced digital circuits. However, in this work we focus on trading-off and improvement of analog circuit performances. Three dif... » read more

The Return Of Body Biasing
By Ann Mutschler - 15 Nov, 2017 - Comments: 1

Body biasing is making a comeback across a wide swath of process nodes as designers wrestle with how to build mobile devices with more functionality and longer battery life. Consider an ultra-low-power IoT device with a wireless sensor, for example, which is meant to last for years without changing a battery. Body biasing can be used to create an ultra-low-leakage sleep state. “In that ... » read more

Automated Body Bias Validation For High Performance, Low Power Electronics
By Mentor, a Siemens Business - 11 Oct, 2017 - Comments: 0

Using a device’s body bias effect allows designers to tune a circuit’s behavior to meet both power and performance specifications, but getting it right isn’t always easy. Accurate, fast, automated body bias verification is critical to ensure today’s complex designs meet demanding performance, reliability, and power usage specifications. To read more, click here. » read more

Inside FD-SOI And Scaling
By Mark LaPedus - 15 Jun, 2017 - Comments: 5

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more

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