tag: Breker Verification Systems

Adapting To Broad Shifts Essential In 2022
By Brian Bailey - 21 Dec, 2022 - Comments: 0

Change creates opportunity, but not every company is able to respond quickly enough to take advantage of those opportunities. Others may respond too quickly, before they properly understand the implications. At the start of a typical year, optimism is in plentiful supply. Any positive trend is seen as continuing, and any negative is seen as turning around. Normally the later in the year that... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Dec, 2022 - Comments: 0

Power always has been a function of cost. The more power required, the more it costs to run a device, both in dollars and carbon footprint. This makes the breakthrough in fusion ignition at Lawrence Livermore National Laboratory all the more noteworthy, and one that could have significant implications for the future of computing, from data centers to rechargeable batteries in automobiles, robot... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 Jul, 2022 - Comments: 0

Tools & IP Cadence will acquire Future Facilities, a provider of electronics cooling analysis and energy performance optimization solutions for data center design and operations using physics-based 3D digital twins. Future Facilities’ product portfolio includes an electronics thermal solution, as well as computational fluid dynamics (CFD) electronics cooling simulation technology that op... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Jul, 2022 - Comments: 0

Tools, IP, design Infineon Technologies acquired NoBug, a provider of design verification services. The acquisition will help Infineon expand its IoT R&D business in eastern Europe. “This considerable increase in superior verification know-how lets Infineon offer its customers more of its leading products at a reduced time-to-market,” said Guenter Krasser, Vice President and Managing D... » read more

AI-Powered Verification
By Brian Bailey - 01 Jun, 2022 - Comments: 1

With functional verification consuming more time and effort than design, the chip industry is looking at every possible way to make the verification process more effective and more efficient. Artificial intelligence (AI) and machine learning (ML) are being tested to see how big an impact they can have. While there is progress, it still appears to be just touching the periphery of the problem... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Mar, 2022 - Comments: 0

Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

The High But Often Unnecessary Cost Of Coherence
By Brian Bailey - 22 Dec, 2021 - Comments: 3

Cache coherency, a common technique for improving performance in chips, is becoming less useful as general-purpose processors are supplemented with, and sometimes supplanted by, highly specialized accelerators and other processing elements. While cache coherency won't disappear anytime soon, it is increasingly being viewed as a luxury necessary to preserve a long-standing programming paradig... » read more

Portable Stimulus And Digital Twins
By Brian Bailey - 25 Nov, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with  Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemens Business; Tom Anderson, technical marketing consultant for OneSp... » read more

The Growing Impact Of Portable Stimulus
By Brian Bailey - 26 Sep, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

Synthesizing Hardware From Software
By Brian Bailey - 22 Aug, 2019 - Comments: 1

The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy