The Week In Review: Design/IoT


Tools Mentor Graphics rolled out a new version of its tool for transferring PCB designs into data for fabrication, assembly and test. The company also announced that its debug environment will support the UPF Low Power Successive Refinement Methodology. Deals Ansys and Cray are claiming the world's record for simulation by scaling 129,000 cores. That's about 4X the previous record.  Ansys... » read more

Software-Driven Verification


[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Tools And Flows In 2015


This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

Software-Driven Verification


[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Problems Lurk In SoC Boundaries


Interfaces always have been a problem, because only rarely does anyone have responsibility for them. Responsibilities generally are tied to functional blocks with the prevailing notion that if all blocks do the right thing, they will also behave correctly when brought together. Design teams that believe this eventually find out the fallacy of this assumption. To make matters worse, these are of... » read more

An Architectural Choice Overdue For Change


The past appears to be a lot simpler than the present and when we look into the future, the right decisions often look highly uncertain. This is the value of hindsight, but also includes the notion that the winner gets to write history. What semiconductors look like today could have been very different if different decisions had been made 20 years ago. What if the industry had adopted a paralle... » read more

Blog Review: July 23


Mentor’s John Day says that within the decade you will be able to contact a real person from your car. Hopefully that doesn't mean marketing people will be able to contact you while you’re stuck in traffic. Cadence’s Brian Fuller says the future of EDA in the automotive market isn’t just about chips. Think security, software and cost reduction. It’s not just SoCs that are going ... » read more

Executive Insight: Adnan Hamid


Semiconductor Engineering sat down with Adnan Hamid, founder and CEO of Breker Verification Systems. Breker was founded in 2003 and has been concentrating on the creation of verification methodologies for multiprocessor SoCs using graph-based entry methods – something that became a hot topic at DVCon 2014 after Mentor Graphics decided to donate its format to Accellera for standardization. ... » read more

Blog Review: May 14


Ansys’ Bill Vandermark highlights the top five engineering articles of the week. Of particular note is element No. 117, a new entry in the periodic table. The temporary name is ununseptium, which means…well, surprise…117. Cadence’s Brian Fuller follows a panel discussion about the biggest potential roadblock for the IoT’s success—privacy and security. You’ve been warned. Syn... » read more

Graphing Toward Standardization


Graph-based verification has become the hot topic of the day. It commanded a lot of attention at the recent DVCon, promises to fix many of the problems plaguing functional verification, can provide an automated way to perform system-level verification, enables portability of tests between simulation, emulation and prototyping, reduces the wastage created by constrained random test pattern gener... » read more

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