Trimming Waste In Chips


Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

Prototypes Proliferate


Hardware prototyping and [getkc id="30" kc_name="emulation"] have been two sides of the same coin ever since the [gettech id="31071" comment="FPGA"] became a commercial success. Early emulators were all built from FPGAs, and most were used in-circuit, much like prototypes are today. More recently, emulation has become a major piece of the [getkc id="10" kc_name="verification"] flow, to the poin... » read more

System Coverage Undefined


When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it's the one verification engineers lose sleep over. Exhaustive [getkc id="56" kc_name="coverage"] has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block... » read more

Portable Stimulus Status Report


The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two decades. [getentity id="22028" e_name="Accellera"] uncorked the PS Early Adopter release at the Design Automation Conference (DAC) in June. The standard has been more than two years in the making by t... » read more

Is Design Innovation Slowing?


Paul Teich, principal analyst for Tirias Research, gave a provocative talk at the recent DAC conference entitled, "Is Integration Leaving Less Room for Design Innovation?" The answer isn't as simple as the question might suggest. "Integration used to be a driver for increasing the functionality of silicon," Teich said. "Increasingly, it will be used to incorporate more features of an entire ... » read more

Verification Unification


Semiconductor Engineering brought together industry luminaries to initiate the discussion about the role that formal technologies will play with the recently released early adopter's draft of Portable Stimulus and how it may help to bring the two execution technologies closer together. Participating in this roundtable are Joe Hupcey, verification product technologist for [getentity id="22017" e... » read more

Verification Unification


Semiconductor Engineering brought together industry luminaries to initiate the discussion about the role that formal technologies will play with Portable Stimulus and how it may help to bring the two execution technologies closer together. Participating in this roundtable are Joe Hupcey, verification product technologist for [getentity id="22017" e_name="Mentor, a Siemens Business"]; Tom Fitzpa... » read more

Safety Plus Security: A New Challenge


Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

Verification Cowboys


There was an event at DVCon that was both fun and serious. It was a panel of verification startup executives with the title "Ride with the Verify Seven." Many of you know [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"] who were the sponsors of the event, along with [getentity id="22914" e_name="ESD Alliance"], the organizat... » read more

Respecting Reset


Resets are a necessary part of all synchronous designs because they allow them to be brought into a known state. However, such a simple process can lead to many problems within an [getkc id="81" kc_name="SoC"]. No longer can reset be considered a simple operation when power initially is applied to a circuit. Instead, the design of reset has many implications on cost, area and routability, a... » read more

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