Finding Defects Is Getting Harder


Chipmakers are plotting out a strategy to scale the transistor to 10nm and beyond. Migrating to these nodes presents a number of challenges, but one issue is starting to gain more attention in the market—killer defects. Defects have always been problematic in the yield ramp for chip designs, but the ability to find them is becoming more difficult and expensive at each node. And it will be... » read more

Speeding Up E-beam Inspection


Wafer inspection, the science of finding killer defects in chips, is reaching a critical juncture. Optical inspection, the workhorse technology in the fab, is being stretched to the limit at advanced nodes. And e-beam inspection can find tiny defects, but it remains slow in terms of throughput. So to fill the gap, the industry has been working on a new class of multiple beam e-beam inspectio... » read more

Flash Dance For Inspection And Metrology


Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

Wanted: Multi-beam E-Beam Inspection


The IC industry is making a giant leap from planar devices to a range of next-generation architectures, such as 3D NAND and finFETs. But it’s taking longer than expected to ramp up these new technologies in the market. And the challenges are expected to mount for the next round of chips. It’s difficult to pinpoint the exact issues with 3D NAND and finFETs. On the manufacturing front alo... » read more