tag: Bruker

Progress In Wafer And Package Level Defect Inspection
By Anne Meixner - 09 Apr, 2024 - Comments: 0

The technology to enable sampling and the need for more metrology and inspection data in a production setting have aligned just in time to address the semiconductor industry’s newest and most complex manufacturing processes. In both wafer and assembly manufacturing, engineering teams have long relied on imaging tools to measure critical features and to inspect for defects after specific pr... » read more

AI/ML Challenges In Test and Metrology
By Gregory Haley - 12 Mar, 2024 - Comments: 0

The integration of artificial intelligence and machine learning (AI/ML) into semiconductor test and metrology is redefining the landscape for chip fabrication, which will be essential at advanced nodes and in increasingly dense advanced packages. Fabs today are inundated by vast amounts of data collected across multiple manufacturing processes, and AI/ML solutions are viewed as essential for... » read more

Laser Wavelength Selection In Raman
By Inga Koehler - 12 Mar, 2024 - Comments: 0

Laser wavelength selection, a critical determinant of accuracy and data quality, is guided by factors such as resonance, fluorescence, and sample absorption. Ensuring the correct laser wavelength leads to optimal excitation and signal strength, facilitating precise and informative analysis. Luminous evolution In the early days of Raman spectroscopy, light sources like arc lamps and incan... » read more

Chip Industry Week In Review
By The SE Staff - 08 Mar, 2024 - Comments: 0

By Adam Kovac, Gregory Haley, and Liz Allan. Cadence plans to acquire BETA CAE Systems for $1.24 billion, the latest volley in a race to sell multi-physics simulation and analysis across a broad set of customers with deep pockets. Cadence said the deal opens the door to structural analysis for the automotive, aerospace, industrial, and health care sectors. Under the terms of the agreement, 6... » read more

Blog Review: Feb. 14
By Liz Allan - 14 Feb, 2024 - Comments: 0

Siemens’ Dilan Heredia and Karen Chow explain why fast, accurate parasitic extraction (PEX) is essential to design success, especially for the 3 nm node and GAAFETs. Synopsys’ Srinivas Velivala debunks the myth that layout-versus-schematic (LVS) checking is a static step in the chip development process, and details its evolving role in modern SoCs. Cadence’s Mark Seymour digs into a... » read more

Chip Industry Week In Review
By The SE Staff - 09 Feb, 2024 - Comments: 0

By Jesse Allen, Linda Christensen, and Liz Allan.  The Biden administration plans to invest more than $5B  for semiconductor R&D and workforce support, including in the National Semiconductor Technology Center (NSTC), as part of the rollout of the CHIPS Act. Today's announcement included at least hundreds of millions for the NSTC workforce efforts, including creating a Workforce Cente... » read more

Hidden Costs And Tradeoffs In IC Quality
By Gregory Haley - 08 Feb, 2024 - Comments: 0

Balancing reliability against cost is becoming more difficult for semiconductor test, as chip complexity increases and devices become more domain-specific. Tests need to be efficient and effective without breaking the bank, while also ensuring chips are of sufficient quality for their specific application. The problem is that every new IC device adds its own set of challenges, from smaller f... » read more

FTIR On Earth, Mercury In Focus
By Xia Stammer - 08 Feb, 2024 - Comments: 0

On early hours on 19th October 2018 at Guiana Space Centre in Kourou in French Guiana an Ariane 5 rocket successfully launched the BepiColombo mission. It started its 7 years journey to Mercury. The joined mission of the European Space Agency (ESA) and the Japan Aerospace Exploration Agency (JAXA) was named in honor of Giuseppe “Bepi” Colombo, an Italian scientist who studied Mercury and fi... » read more

Inspection, Metrology Issues In Advanced Packages
By Gregory Haley - 08 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about how to inspect and measure smaller features across large areas in advanced packaging, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; John Hoffman, computer vision engineering manager at Nordson Test & Measurement; and Jiangtao Hu, senior technology director at O... » read more

Chip Industry Week In Review
By The SE Staff - 02 Feb, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan. Cadence introduced an AI-based thermal stress and analysis platform aimed at 2.5D and 3D-ICs, and cooling for PCBs and electronic assemblies. The company also debuted a HW/SW accelerated digital twin solution for multi-physics system design and analysis, combining GPU-resident computational fluid dynamics (CFD) solvers with dedicated GPU hardwar... » read more

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