Supporting CPUs Plus FPGAs


While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

The Week In Review: Design


Tools Synopsys revealed a comprehensive low power reference kit for design and verification based on a bitcoin mining SoC design. The kit is designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology and as a learning vehicle for the complete Synopsys low power flow. Space Codesign introduced the latest version of its simulation environmen... » read more

Challenges Grow For IP Reuse


As chip complexity increases, so does the complexity of IP blocks being developed for those designs. That is making it much more difficult to re-use IP from one design to the next, or even to integrate new IP into an SoC. What is changing is the perception that standard [getkc id="43" kc_name="IP"] works the same in every design. Moreover, well-developed [getkc id="100" kc_name="methodologie... » read more

The CEO Outlook Returns


One of the more popular events hosted by the EDA Consortium (EDAC, to those in the know) was the CEO Forecast held at the start of each year. It was phased out several years ago for a number of reasons, including logistics and scheduling. Attendance was never one of them. As I took the reins of EDAC two years ago, I repeatedly heard how much that evening was missed. Members and non-members h... » read more

Carving Up Verification


Anirudh Devgan, executive vice president and general manager of [getentity id="22032" e_name="Cadence's"] System & Verification Group, sat down with Semiconductor Engineering to discuss the evolution of verification. What follows are excerpts of that conversation. SE: What’s changing in [getkc id="10" kc_name="verification"]? Devgan: Parallelism, greater capacity and multiple engine... » read more

Blog Review: March 22


Cadence's Paul McLellan shares TSMC's plans for 5nm and gate-all-around FET, plus other highlights from last week's Technology Symposium. Mentor's Craig Armenti examines how product development teams can increase efficiency through concurrent schematic design. Synopsys' Jim Ivers warns of the data security and privacy issues posed by a wave of popular connected toys. At Embedded World,... » read more

The Week In Review: Manufacturing


Chipmakers At this week’s TSMC Technology Symposium in San Jose, Calif., TSMC rolled out a dizzying array of new processes and technologies. Perhaps the most surprising announcement was a 22nm bulk CMOS process, which is geared for ultra low-power planar chips. The technology will compete against a 22nm FD-SOI technology from GlobalFoundries. Stay tuned. The battle has just begun. As e... » read more

The Week In Review: Design


Business Andes Technology went public this week on the Taiwan Stock Exchange with an initial stock listing of 40,611,915 shares at a price of NT$65.10 (USD $2.12) per share. The shares began trading March 14, 2017, under the TWSE ticker symbol “6533.TWO.” Andes plans to use the proceeds to expand the company's R&D effort, to fuel international expansion into the U.S. and Europe and t... » read more

MEMS Microphones: A Bright Spot Among Commoditized Consumer Sensors


MEMS microphones have emerged as a bright spot among consumer sensors, which in general are going through a rapid commoditization and profit-squeezing trend. To understand what’s driving the MEMS microphone market, consider that the Apple iPhone 7 and 7S each have 4 MEMS microphones. As reported by System Plus Consulting, the latest iPhones have “a front-facing top microphone, presumably f... » read more

Power Impacting Cost Of Chips


The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

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