Manufacturing Bits: June 6


Molecular black holes A group of researchers have used an ultra-bright pulse of X-ray light to hit a tiny atom in a molecule, causing the structure to explode and create a “molecular black hole.” The molecular black hole is different than a black hole in space, however. A black hole is a region in space, which has a gravitational field so strong that no matter or light can escape it. ... » read more

Better Code With RTL Linting And CDC Verification


Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

Powerful New Standard


In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

Blog Review: Jan. 13


Is it time for one of the Seven Wonders to return? In this week's top engineering and tech picks, Ansys' Justin Nescott highlights a project to rebuild the Colossus of Rhodes. Plus, new tech for cars and a hoodie for taking naps. From CES, Rambus' Aharon Etengoff expands on a talk about intelligent transportation systems and the need to balance technology which could help reduce accidents wi... » read more

Verification Grows Up


Semiconductor Engineering sat down with a group of verification experts to see how much progress has been made in solving issues associated with the profession. Panelists included Mike Baird, president of Willamette HDL; Jin Zhang, VP marketing and customer relations for [getentity id="22147" comment="Oski Technology"], and Lauro Rizzatti, a marketing consultant and previously the general manag... » read more

The Problem With CDCs


Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with multiple asynchronous clocks which necessitates using advanced verification techniques targeting anomalies related to clock domain crossings (CDCs). Typical electronic design automation (EDA) tools f... » read more

Developing High-Reliability FPGAs For DO-254


You have been developing FPGAs for a long time, and you know your designs from top to bottom. You know every interface protocol, configuration and optimization. You can visualize your timing diagram like you can visualize your upcoming vacation in Hawaii. You can manually write down your memory mapping accurately while under oath. You can pinpoint all CDC paths and emulate metastability in your... » read more

Next-Generation Power-Aware CDC Verification: What Have We Learned?


Reducing power consumption is essential to mobile and handheld application chips where reduced power contributes to longer battery life while minimally impacting performance. Reduced power consumption is achieved by partitioning an ASIC into multiple power domains, then controlling the power of these domains by switching off power or reducing voltage levels. Reduction of power consumption is fu... » read more

When Things Go Wrong Even When You’re Doing the Right Thing


By Kurt Takara and Joe Hupcey III “Isolation. Retention. Level shifters. Dynamic voltage scaling. I’m doing all the right things to reduce the power consumption of my design by adding all of this power control logic. But because of this new low power circuitry, I’m seeing fresh clock domain crossing (CDC) problems that are making my design do all the wrong things; and my trusty old low... » read more

Clock Domain Crossing (CDC): Are We There Yet?


Over the last decade, SoC designs have become significantly reliant on IP reuse to manage the design complexity and meet time-to-market goals. IP-based design and verification methodology is essential but has put an additional verification burden on IP suppliers (internal and external). IP suppliers need to ensure that their IP is exhaustively verified and SoC Integrators need to ensure that al... » read more

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