An Introduction To Reducing Dynamic Power

In the past few blogs we have been primarily talking about UPF and applying the Successive Refinement process to save power. But, this process addresses leakage power. In this session we want to talk about how to save dynamic power. As designs move to finFET technology, dynamic power is the dominant contributor to power consumption. Power consumption trend. I recently sat down with my c... » read more

Micro-Architectural Exploration For Low Power Design

By Abhishek Ranjan, Saurabh Shrimal and Sanjiv Narayan In the first part of this series, we discussed the need to perform power optimizations and exploration at higher levels of abstractions, where the potential to reduce the power consumption was highest. While fine-grained local changes (like clock-gating, operand isolation, etc.) for power reduction are well understood and widely adopted,... » read more

A Strategy For Designing For Power With FinFETs

Recently Qualcomm announced their new SnapDragon processor 820, which was designed using finFET technology. They showed some amazing results, such as 2X improvement in performance and 2X improvement in power compared to 28nm designs. Previously, when ARM announced their A72 processors in finFET, they too had claimed 3.5X improvement in power compared to 28nm designs. But can designers expect... » read more

Power Breaks Everything

The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

Asynchronous Design: Is It Time Yet?

Non-mainstream technologies can offer advantages over more commonly used approaches, but usually at some additional cost (otherwise they’d probably be mainstream). The additional cost could be in design time, area, testability or whatever, and it might even be only a temporary disadvantage. If comparable time and energy were invested in the new technology, perhaps the additional costs would d... » read more

Are More Processor Cores Better?

Up until the early 2000s, each generation of processor was faster, used more exotic architectures, had deeper pipelines, used more transistors, ran at higher clock frequencies and consumed more power. In fact power was rising faster than performance and led to the extrapolation that within a few generations, processors would run as hot as nuclear reactors. Something had to change, and that c... » read more

Can HLS Be Trusted?

Semiconductor Engineering sat down with Mike Meredith, solutions architect at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. Part 1 of the discussion looked at the changing market for HLS and the types of customers who are adopting HLS today. Divi... » read more

Clock Gating Optimization At RTL

In today’s semiconductor designs, lower power consumption is mandatory for mobile and hand-held applications for longer battery life and for networking or storage devices for low carbon footprint requirements. Clock power can consume as much as 60% to 70% of total chip power and is expected to increase further in the more advanced technology nodes. Hence, reducing clock power is very importan... » read more

What’s Next For Power Optimization

Today it is difficult to find a design that does not consider some kind of power optimization. Mobile needs it to preserve battery life, data centers need it to reduce operating cost, and many are finding they need it to meet tougher regulatory requirements. In a survey conducted two years ago, there was no segment of the industry that was not taking a serious look at reducing their power profi... » read more

Smarter Clock Gating

By Ghulam Nurie With the proliferation of mobile devices, power consumption and battery life have emerged as significant concerns during chip design. There are many different techniques used for power optimization, but of all the different techniques, clock gating is the most popular and widely used technique, according to a blind, anonymous survey emailed to several thousand participants worl... » read more

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