SCREAMER: A Demonstrator Chip For Spectral Noise Optimization By Clock Latency Scheduling

This paper outlines the design and measurement of a 130 nm test chip named SCREAMER for reducing the digital switching noise in synchronous circuits. Clock latency scheduling has been investigated as a means to optimize switching noise in the frequency domain through PDN simulation. Integrated in parallel on the chip are four instances of a test design, each addressing a distinct strategy of cl... » read more

The Trouble With Clock Trees

By Arvind Narayanan Among the perennial challenges of advanced-node IC design is power reduction. Clock trees are now the single largest source of dynamic power consumption, which makes clock tree synthesis (CTS) and optimization an important task for achieving overall power savings. Building a well-balanced clock tree and effectively managing clock skew has been a challenge since the first... » read more