IC Manufacturing Targets Less Water, Less Waste


Fabs, OSATs, and equipment makers are accelerating their efforts to consume less water while recycling more material waste in a trend toward better sustainability. With chips, sustainability is heavily focused on carbon emissions, and energy consumption is a significant contributor. But there is an equal effort underway to reduce water consumption and pollution. Across the globe, the number ... » read more

Analysis Of BEOL Metal Schemes By Process Modeling


The semiconductor industry has been diligently searching for alternative metal line materials to replace the conventional copper dual damascene scheme, because as interconnect dimensions shrink, the barrier accounts for an increasing fraction of the total line volume. The barrier layer's dimensions cannot be scaled down as quickly as the metal line width (figure 1). Popular barrier materials su... » read more

Blog Review: November 15


Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

The Impact Of Channel Hole Profiles On Advanced 3D NAND Structures


In a two-tier 3D NAND structure, the upper and lower channel hole profile can be different, and this combination of different profiles leads to different top-down visible areas. The visible area is the key metric to determine whether the bottom SONO layer can be punched through and ensure that the bit cells connect to the common source line. Performing channel hole profile splits on a silicon w... » read more

Securing Chip Manufacturing Against Growing Cyber Threats


Semiconductor manufacturers are wrestling with how to secure a highly specialized and diverse global supply chain, particularly as the value of their IP and their dependence upon software increases — along with the sophistication and resources of the attackers. Where methodologies and standards do exist for security, they often are confusing, cumbersome, and incomplete. There are plenty of... » read more

Chip Industry’s Technical Paper Roundup: August 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=39 /] More Reading Technical Paper Library home » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology


A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

Improving Gate All Around Transistor Performance Using Virtual Process Window Exploration


As transistor sizes shrink, short channel effects make it more difficult for transistor gates to turn a transistor ON and OFF [1]. One method to overcome this problem is to move away from planar transistor architectures toward 3D devices. Gate-all-around (GAA) architectures are an example of this type of 3D device [2]. In a GAA transistor, the gate oxide surrounds the channel in all directions.... » read more

Balancing AI And Engineering Expertise In The Fab


Modeling and simulation are playing increasingly critical roles in chip development due to tighter process specs, shrinking process windows, and fierce competition to bring technologies to market first. Before a new device makes it to high-volume manufacturing, there are countless engineering hours spent on developing the lithography, etching, deposition, CMP, and many other processes, at hi... » read more

Blog Review: June 21


Synopsys' Vikram Bhatia identifies four trends driving the migration of EDA tools and chip design workloads to the cloud, from ever-increasing compute and time-to-market demands to advanced cybersecurity features. Cadence's Veena Parthan checks out how computational fluid dynamics and finite element analysis can help improve aquaculture with sustainable fish cage nets that minimize stagnatio... » read more

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