Mixed-signal/Low-power Design

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

Automated Power Model Verification For Analog IPs

By Sierene Aymen and Hartmut Marquardt Creating macro power models for analog intellectual property (IP) blocks is essential to enable the chip assembly group to effectively integrate these blocks within their place and route environment. These macro models, which define power domains, identify IP ports as signal, power, ground, or trivial ports, and describe the associations of signal pins ... » read more

Mentor, Cadence Join Forces

Mentor Graphics and Cadence have agreed to create a single binary interface for their respective simulation and emulation platforms, allowing debug tools from one vendor to run on the other's platforms. The two have invited [getentity id="22035" e_name="Synopsys"] to join their initiative, as well. So far, there is no decision. The move proposes a single API for both [getentity id="22032"... » read more

Formal Low-Power Verification Of Power-Aware Designs

Power reduction and management methods are now all pervasive in system- on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design th... » read more

Power Management Verification Requires Holistic Approach

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

Unraveling Power Methodologies

When working on articles, the editors at Semiconductor Engineering sometimes hear things that make them stand back and question what seems to be an industry truth. One such statement happened last month while researching a different article. The statement was: Most designs are not top-down, but in fact bottom-up when it comes to power management. The most used methodology today is that the RTL... » read more

Balancing The Cost Of Test

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

Energy Boost For Power Standards

If the amount of standards work and industry effort that is being expended on a given topic is any indicator of the growing importance of a design concern, then power has most certainly become the hottest topic in the industry. Thankfully, it seems as if everyone has learned their lessons from the CPF/[gettech id="31044" t_name="UPF"] struggles and is attempting to coordinate activities, while ... » read more

Reduced Power To The People!

Fifteen years ago, many of us involved in writing the design chapter of the ITRS (International Technology Roadmap for Semiconductors) already knew that power/energy consumption eventually would become a major problem for the industry’s growth. Engineers developing microprocessors (CPUs and DSPs) and graphics engines (GPUs) led the wave of predictions, because extrapolating known trend data s... » read more

Know What To Look For

With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

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