Power Challenges At 10nm And Below


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

MediaTek Grabs Another Gear


Today, it seems to be all the rage for automotive manufacturers to try to continuously one up the competition by announcing a new transmission that has more gears or “speeds." (Popular Mechanics did a nice article about why you would want more gears.) Basically, transmission designers want to keep the engine operating at or near its peak operating efficiency point and extend the operating ran... » read more

Top Articles For 2015 In SLD And LPHP


Knowing your readership is the first step in being able to serve them better, and judging by the traffic increases this year, we must be doing quite a few things right. We have now completed our second full year and the first full year for the Knowledge Center (KC). We are pleased with the way in which the two are playing together but there is still a lot of work ahead of and many holes to fill... » read more

Performance Analysis On Dark Silicon


It’s one thing to do performance analysis on the ‘light’ parts of an SoC design, but what about when most of the silicon is ‘dark?’ Jon McDonald, technical marketing engineer at Mentor Graphics stressed that modeling the effects of turning on and off sections of the silicon is an important part of creating an accurate representation of the system. “Our models support state-based... » read more

Rethinking Power


Power typically has been the last factor to be considered in the PPA equation, and it usually was somebody else's problem. Increasingly it's everyone's problem, and EDA companies are beginning to look at power differently than in the past. While the driving forces vary by market and by process node, the need to save energy at every node and in almost all designs is pervasive. In the server m... » read more

One-On-One: Dark Possibilities


Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. (P... » read more

One-On-One: Dark Servers


Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. To... » read more

One-On-One: Dark Silicon


Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. (F... » read more

Fighting Dark Silicon With Specialized Hardware


Looking at an SoC design from an architecture viewpoint, I’m hearing more discussion lately about the option of offloading tasks to specialized hardware. Especially where dark silicon is concerned, rather than having four or eight ARM processors — all with the same complexity — or cores like graphics processors, if you cannot use them all at full performance and they have to be shut o... » read more

Is Dark Silicon Wasted Silicon?


The concept of dark silicon sounds almost mysterious, but it is a simple matter of physics. With advances in technology nodes and the ability to pack more and more transistors on the same die, design engineers are reaching a wall where only a fraction of a design can be powered on due to power and thermal implications. Moreover, the challenges that force this kind of complex power managemen... » read more

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