tag: debug

Overcoming Regression Debug Challenges With Machine Learning
By Robert Ruiz - 22 Jun, 2023 - Comments: 0

Development of a modern semiconductor requires running many electronic design automation (EDA) tools many times over the course of the project. Every stage, from architectural exploration and design to final implementation and manufacturing preparation, has multiple methodology loops that must be repeated again and again. Even in such a complex development flow, functional simulation stands ... » read more

How Chip Engineers Plan To Use AI
By Ed Sperling - 19 Apr, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how AI is being used today and how engineers expect to use it in the future, with Michael Jackson, corporate vice president for R&D at Cadence; Joel Sumner, vice president of semiconductor and electronics engineering at National Instruments; Grace Yu, product and engineering manager at Meta; and David Pan, professor in the ... » read more

RISC-V Driving New Verification Concepts
By Brian Bailey - 12 Apr, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

What’s Required To Secure Chips
By Ed Sperling - 06 Apr, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about how to verify that a semiconductor design will be secure, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketing at Expedera; and Dave Kelf, CEO of Breker Verification. ... » read more

Advanced Digital Process Nodes Drive Semiconductor Test Innovations
By Regan Mills - 07 Mar, 2023 - Comments: 0

Global internet traffic is growing exponentially, with no sign of slowing, and this demand is driving the evolution of the semiconductor industry. The appetite for more and more data requires sensors for capturing the data, networks for moving the data, storage, and processing power to analyze the data. As the demand for data grows, the underlying technologies must advance to not only meet toda... » read more

Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking
By Siemens EDA - 22 Feb, 2023 - Comments: 0

Early-stage layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows that require correct connectivity for valid results. The Calibre nmLVS Recon tool targets essential and relevant early-stage circuit verification pain points, such as electrical rule checking (ERC) ... » read more

Using Machine Learning To Automate Debug Of Simulation Regression Results
By Synopsys - 08 Feb, 2023 - Comments: 0

Regression failure debug is usually a manual process wherein verification engineers debug hundreds, if not thousands of failing tests. Machine learning (ML) technologies have enabled an automated debug process that not only accelerates debug but also eliminates errors introduced by manual efforts. This white paper discusses how verification engineers can more efficiently analyze, bin, triage... » read more

Achieve 10X Faster CDC Debug Leveraging Machine Learning
By Synopsys - 25 Jan, 2023 - Comments: 0

Over the years, system-on-chip (SoC) design sizes have crossed the billion-gate mark. Higher complexity has been introduced within semiconductor designs to deliver desired functionality. The number of asynchronous clock and reset domains is growing heavily within these complex SoCs, leading to millions of clock domain crossing (CDC) violations at the SoC level. Each of these violations ... » read more

Design And Verification Methodologies Breaking Down
By Brian Bailey - 12 Jan, 2023 - Comments: 0

Tools, methodologies and flows that have been in place since the dawn of semiconductor design are breaking down, but this time there isn't a large pool of researchers coming up with potential solutions. The industry is on its own to formulate those ideas, and that will take a lot of cooperation between EDA companies, fabs, and designers, which has not been their strong point in the past. It ... » read more

Efficient Trace In RISC-V
By Ed Sperling - 19 Dec, 2022 - Comments: 0

Systems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks about what's needed for debug and trace in context, including the need for unobtrusive observation at full speed, what to trace and when to trace it, and how embedded IP can identify to report which branches are tak... » read more

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