Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors


Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more

A Bare Wafer Mystery: Inspecting For Back, Edge, And Notch Defects In Advanced Nodes


It is no mystery that the semiconductor industry is always advancing, with specifications becoming increasingly stringent as defects become increasingly more difficult to discover. This is especially true in the case of the most advanced nodes, where ever-smaller flaws and deformities can result in a killer defect. To solve this More than Moore mystery, you do not need to employ the detectiv... » read more

Predicting Defect Properties In Semiconductors With Graph Neural Networks


A technical paper titled “Accelerating Defect Predictions in Semiconductors Using Graph Neural Networks” was published by researchers at Purdue University, Indian Institute of Technology (IIT) Madras, GE Research, and National Institute of Standards and Technology (NIST). Abstract: "Here, we develop a framework for the prediction and screening of native defects and functional impurities i... » read more

5 Reasons Why Defect Reduction Is Critical In Semiconductor Material Success


Semiconductors may be small, but the impacts they have are significant. Semiconductors used in life-dependent applications, such as pacemakers, defibrillators, life support systems, automotive safety systems, or in aviation need to be fail-proof. A device smaller than a centimeter with features just a few nanometers has no margin of error. This blog shares why it’s important to detect materia... » read more

SiC Growth For EVs Is Stressing Manufacturing


The electrification of vehicles is fueling demand for silicon carbide power ICs, but it also is creating challenges in finding and identifying defects in those chips. Coinciding with this is a growing awareness about just how immature SiC technology is and how much work still needs to be done — and how quickly that has to happen. Automakers are pushing heavily into electric vehicles, and t... » read more

Striking A Balance In Acoustic Inspection


Sound energy is a quick way to to spot voids, delamination, cracks, and other possible defects that are accessible from outside the chip or package, as well as some defects that are inside of chips. But acoustic inspection also is highly sensitive to different materials with different polarities, which can change the reflection of sound waves. Bill Zuckerman, product marketing manager at Nordso... » read more

Journey From Cell-Aware To Device-Aware Testing Begins


Early results of using device-aware testing on alternative memories show expanded test coverage, but this is just the start. Once the semiconductor industry realized that it was suffering from device failures even when test programs achieved 100% fault coverage, it went about addressing this disconnect between the way defects manifest themselves inside devices and the commonly used fault mod... » read more

Ramping Up Power Electronics For EVs


The rapid acceleration of the power devices used in electric vehicles (EVs) is challenging chipmakers to adequately screen the ICs that power these vehicles.[1] While progress toward autonomous driving is grabbing the public’s attention, the electrification of transportation systems is progressing quietly. For the automotive industry, this shift involves a mix of electronic components. Amo... » read more

Data Analytics For The Chiplet Era


This article is based on a paper presented at SEMICON Japan 2022. Moore’s Law has provided the semiconductor industry’s marching orders for device advancement over the past five decades. Chipmakers were successful in continually finding ways to shrink the transistor, which enabled fitting more circuits into a smaller space while keeping costs down. Today, however, Moore’s Law is slowin... » read more

EUV Lithography: Results of Single Particle Volume Charging Processes in EUV Exposure Environment With Focus On Afterglow Effects


A new technical paper titled "Particle charging during pulsed EUV exposures with afterglow effect" was published by researchers at ASML, ISTEQ B.V., and Eindhoven University of Technology. Abstract "The nanoparticle charging processes along with background spatial-temporal plasma profile have been investigated with 3DPIC simulation in a pulsed EUV exposure environment. It is found that the ... » read more

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