tag: delay insensitivity

Making Waves In Low-Power Design

By Barry Pangrle - 16 Jan, 2014 - Comments: 0

Barry Pangrle In a blog last April we looked at a potential candidate technology that just might be able to produce an economically feasible method for implementing delay insensitive circuits in CMOS. The basic idea behind this technology has been around since at least the 1990s and is better known as Null Convention Logic™ (NCL). Much of the work in this area was pioneered by Karl Fant and ... » read more

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