Analog Fault Simulation Challenges And Solutions

The test time for digital circuit blocks in ICs has greatly decreased in the last 20 years, thanks to scan-based design-for-test (DFT), automatic test pattern generation (ATPG) tools, and scan compression. These technologies have greatly reduced the number of test vectors applied by automatic test equipment (ATE) while maximizing the coverage of a wide range of defect types. But for analog c... » read more

Putting Design Back Into DFT

Test always has been a delicate balance between cost and quality, but there are several changes happening in the industry that might cause a significant alteration in strategy. Part one of this two part series about [getkc id="47" comment="Design for Test (DFT)"] looked at changes in areas such as automotive, where built in self-test is becoming a mandated part of the design process. This co... » read more

Gaps Emerge In Test Flows

Gaps are showing up in test flows as chipmakers add more analog content and push into more safety-critical applications, exposing more points at which designs need to be tested as well as weaknesses in current tools and methodologies. The cornerstone of the [getkc id="76" kc_name="IoT"], and connected devices such as self-driving cars, is a heavy reliance on [getkc id="187" kc_name="sensors"... » read more

New Drivers For Test

Mention Design for Test (DFT) and scan chains come to mind, but there is much more to it than that—and the rules of the game are changing. New application areas such as automotive may breathe new life into built-in self-test (BIST) solutions, which could also be used for manufacturing test. So could DFT as we know it be a thing of the past? Or will it continue to have a role to play? Te... » read more

Accelerating Design-For-Test Pattern Simulation

The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ATPG, BIST, or functional patterns. It enables running complete patterns for DFT verification in a reasonable time to shorten the pattern development cycle. The Veloce DFT App fits seamlessly into the Veloce ecosystem, enabling a ho... » read more

Gate-Level Simulation Methodology

The increase in design sizes and the complexity of timing checks at 40nm technology nodes and below is responsible for longer run times, high memory requirements, and the need for a growing set of gate-level simulation (GLS) applications including design for test (DFT) and low- power considerations. As a result, in order to complete the verification requirements on time, it becomes extr... » read more

SoC Connectivity Verification Nightmare

At the recent 2015 women’s World Cup soccer final in Canada, Japan was completely caught off guard in the first 15 minutes (and 4 seconds) by the USA. They were wary of the “set-piece” play by the USA team, which they were not able to defend against, resulting in the first three goals by the American women. However, the game breaker was the 54-foot midfield hat-trick goal from Carli Lloyd... » read more

Leveraging Physically Aware Design-For-Test To Improve Area, Power, And Timing

Increased pressures on design teams to deliver faster, smaller devices in less time has required EDA companies to develop an integrated methodology to incorporate physical design information during DFT synthesis. This solution must consider the placeable area (or size) of the circuit as well as routing blockages and hard macro placement locations. It must also be able to both model the wiring i... » read more

Divide And Conquer: Hierarchical DFT For SoC Designs

Large System on Chip (SoC) designs present many challenges to all design disciplines, including design-for-test (DFT). By taking a divide-and-conquer approach to test, significant savings in tool runtime and memory consumption can be realized. This whitepaper describes the basic components of a hierarchical DFT methodology, the benefits that it provides, and the tool automation that is availabl... » read more

Balancing The Cost Of Test

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

← Older posts