Accelerating DO-254 Approval


This white paper explores software tools as they relate to meeting the DO-254 Design Assurance Guidance for Airborne Electronic Hardware specifications, and what steps must be performed in order to use your typical design automation tools such as simulation, synthesis, etc. In this paper, we will explore how DO-254 views tools, learn which tools receive the highest scrutiny and why, and how to ... » read more

Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

What Can Go Wrong In Automotive


Semiconductor Engineering sat down to discuss automotive engineering with Jinesh Jain, supervisor for advanced architectures in Ford’s Research and Innovation Center in Palo Alto; Raed Shatara, market development for automotive infotainment at [getentity id="22331" comment="STMicroelectronics"]; Joe Hupcey, verification product technologist at [getentity id="22017" e_name="Mentor Graphics"]; ... » read more

The Real Differences Between HW And SW


How many times have we heard people say that hardware and software do not speak the same language? The two often have different terms for essentially the same thing. What hardware calls constrained random test is what software people call fuzzing. Another one recently caught my eye in a conversation with Jama Software, a Portland software company that has made a name for itself in requiremen... » read more

The Hardest Part Of DO-254 Is…


The hardest part of DO-254 is not the requirements. It’s not the design. It’s not the verification. We just wrapped up this year’s 3-day DO-254 Practitioner’s Course, and each year I learn something new. In this year’s training we had attendees from major aerospace companies including Curtiss Wright, Rolls Royce, Sierra Nevada Corporation, Thales and Woodward. It’s always a pleas... » read more

Planes, Cars, And Lagging Standards


Automotive and aerospace standards are struggling to adapt to pervasive connectivity, increased functionality, and new packaging approaches and architectures, leaving chipmakers and systems vendors unsure about what needs to be included in future designs. Each of these markets has a reputation for being lumbering and unresponsive, in part because they deal with safety-critical issues and i... » read more

Q&A With FAA DO-254


Aldec together with FAA DER Randall Fulton conducted a webinar to provide clarifications on some of the most commonly misunderstood objectives and aspects of DO-254. The following is the list of questions that were submitted to Aldec for the webinar. All questions are related to applying DO-254 to FPGAs and PLDs. The answers from Randall Fulton are provided correspondingly. To read more, c... » read more

Managing Validation And Verification Abstract Activities For DO-254


This paper provides an overview of the Validation and Verification (V & V) process and its associated activities as described in RTCA/DO-254. With the growing size and complexity of today’s FPGAs, managing V & V activities is becoming difficult and time-consuming. This paper presents a list of recommended features, methodologies and capabilities that must be supported by a tool to manage V & ... » read more

Finding CDC Issues Before They Find You


Clock domain crossings (CDCs) in FPGAs represent a probabilistic opportunity for failure. Functional simulation and static timing analysis tools are insufficient. Finding and addressing metastability and data incoherence around CDCs require static and dynamic analysis of FPGA designs. Aldec ALINT-PRO-CDC provides enhanced confidence that CDCs are located and fully mitigated. To read more, cl... » read more

The Problem With CDCs


Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with multiple asynchronous clocks which necessitates using advanced verification techniques targeting anomalies related to clock domain crossings (CDCs). Typical electronic design automation (EDA) tools f... » read more

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