Data Centers Turn To New Memories


DRAM extensions and alternatives are starting to show up inside of data centers as the volume of data being processed, stored and accessed continues to skyrocket. This is having a big impact on the architecture of data centers, where the goal now is to move processing much closer to the data and to reduce latency everywhere. Memory has always been a key piece of the Von Neumann compute archi... » read more

What Happened To ReRAM?


Resistive RAM (ReRAM), one of a handful of next-generation memories under development, is finally gaining traction after years of setbacks. Fujitsu and Panasonic are jointly ramping up a second-generation ReRAM device. In addition, Crossbar is sampling a 40nm ReRAM technology, which is being made on a foundry basis by China’s SMIC. And not to be outdone, TSMC and UMC recently put ReRAM on ... » read more

Four Foundries Back MRAM


Four major foundries plan to offer MRAM as an embedded memory solution by this year or next, setting the stage for what finally could prove to be a game-changer for this next-generation memory technology. GlobalFoundries, Samsung, TSMC and UMC plan to start offering spin-transfer torque magnetoresistive RAM (ST-MRAM or STT-MRAM) as an alternative or a replacement to NOR flash, possibly start... » read more

What Is Spin Torque MRAM?


The memory market is going in several different directions at once. On one front, the traditional memory types, such as DRAM and flash, remain the workhorse technologies. Then, several vendors are readying the next-generation memory types. As part of an ongoing series, Semiconductor Engineering will explore where the new and traditional memory technologies are heading. For this segment, P... » read more

Rethinking Computing Fundamentals


New compute architectures—not just new chips—are becoming a common theme in Silicon Valley these days. The whole semiconductor industry is racing to find the fastest, cheapest, lowest-power approach to processing. The drivers of this shift are well documented. Moore's Law is slowing down, in part because it's becoming more difficult to route signals across an SoC at the latest process no... » read more

Enabling Higher System Performance With NVDIMM-N


The shift from the traditional enterprise data center to the cloud is driving an insatiable demand for increased bandwidth and lower latencies. This is fundamentally reshaping traditional memory, storage, network and computing architectures. Although the semiconductor industry has been innovating to meet the needs of these new architectures, it continues to grapple with a waning Moore’s Law t... » read more

A Tale of Two Testers


David Tacelli, president and CEO of Xcerra, was excited. His company’s reception for customers (and the press) at the Trou Normand restaurant in San Francisco’s hip South of Market neighborhood was going very well. Gourmet salames and other tasty foods were on offer, along with fine wines and craft ales and beers. He gleefully pointed out to editors that the product to be introduced at t... » read more

Rethinking SSDs In Data Centers


Semiconductors that control how data gets on and off solid-state drives (SSDs) inside of data centers are having a moment in the sun. This surge in interest involves much more than just the SSD device. It leverages an entire ecosystem, starting with system architects and design engineers, who must figure out the best paths for data flow on- and off-chip and through a system. It also includes... » read more

Memory Buffer Chips: Satisfying Amdahl’s Law To Sustain Moore’s Law


Moore’s Law, the observation that the available transistors in an integrated circuit doubles every two years, has driven the semiconductor and IT industries to unparalleled growth over the last 50+ years. These transistors have been used in CPUs to increase the number of parallel execution units and instruction fetches, expand the levels of on-chip cache (and overall capacity), support spe... » read more

Start Your HBM/2.5D Design Today


High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. In June 2015, AMD introduced its Fiji processor, the first HBM 2.5D design, which comp... » read more

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