Testing the Big Bang of Smart Devices

Thanks to the proliferation of smart devices in the Internet of Things (IoT), it’s a circumstance not unlike the overwhelming sense of wonder and bewilderment that ancient Greek astronomer Ptolemy must have felt when gazing up at a sky full of stars on a clear winter’s night, trying to rationalize the vast tableau before him. But just as we wouldn’t critique early astronomers and philo... » read more

U.V.M. Spells Relief

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly. So what is UVM? UVM is a verification meth... » read more

UVM: What’s Stopping You?

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

Dealing With The Data Glut

By Ann Steffora Mutschler Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle? Even with an emulator a five-minute mobile phone call could take three months. Understandably, this issue is causing pain to many design teams... » read more