Abstracting Abstracter Abstractions In Functional Verification


I heard a clear three-part message during DVCon at the end of February: verification engineers must abstractly embrace the abstract idea of abstracting abstract abstraction through higher levels of abstraction; we overuse the word abstract to emphasize the value of whatever verification technique we happen to be talking about; and the key to new abstractions is using Portable Stimulu... » read more

Verification And Validation Brothers


At DVCon this year, Doug Amos took the stage for the [getentity id="22017" e_name="Mentor, a Siemens Business"] sponsored lunch presentation. For those of you who were there but decided to skip the lunch, expecting the traditional forced sales pitch, you made a mistake. Amos is one of those rare people who know how to inject humor, teaching and marketing into a single presentation such that the... » read more

The Week In Review: Design


Tools & IP Pro Design launched three new proFPGA Zynq UltraScale+ FPGA modules for SoC and IP prototyping. The modules combine FPGA logic with quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processors and on-board interfaces. The modules offer a total of up to 5 extension sites with 531 standard I/Os and 16 multi-gigabit transceivers (MGTs). The board allows a maximum point-to-point ... » read more

The Week In Review: Design


Tools & IP Arm unveiled a new suite of IP focused on machine learning for edge devices. Currently dubbed Project Trillium, it includes the Arm ML processor, the second-generation Arm Object Detection (OD) processor, and open-source Arm NN software. The ML processor provides more than 4.6 TOPs in mobile environments with efficiency of 3 TOPs/W. People detection is a focus of the OD processo... » read more

The Week In Review: Design


Security Addressing the Meltdown and Spectre speculative execution vulnerabilities has not gone smoothly. Intel's firmware update caused unexpected behavior and a higher than expected number of reboots for its Haswell and Broadwell chips, leading the company to recommend users stop patching until an updated version of the patch is available. Microsoft's attempts to fix the issue left some W... » read more

DVCon Committee Picks


A typical development team contains more verification engineers than design engineers, and that skew is getting wider. You can expect the trend to increase given that verification teams are now getting loaded with added complexity from heterogeneous multi-core systems, functional safety, neural networks and security-in addition to increasing size. Companies that do not keep up with the lates... » read more

The Week In Review: Design


M&A Barco Silex, now named Silex Inside, split from parent company Barco in a management buyout in partnership with a group of private investors lead by Dutch investment company Vehold BV. The company will continue its focus on security, video compression, and interface IP, along with design services. Tools & IP Mentor is making a version of its HyperLynx design rule checking tool ... » read more

The Week In Review: Design


Altium released the latest version of its PCB design suite. Improvements include a new interface and an upgrade to 64-bit architecture combined with multi-threaded task optimizations. Other additions include a new BoM rule checker and length tuning and pin-swapping in the user-guided routing engine. Creonic announced a new line of IP for 5G forward error correction. The product line covers t... » read more

Getting A Standard Right The First Time


The development of standards is a tricky balance, especially when going into areas that are nascent. The [getentity id="22863" e_name="Portable Stimulus Standard"] (PSS), being developed within [getentity id="22028" e_name="Accellera"] is one of those. This could be the most important standard since [gettech id="31017" comment="Verilog"] and [gettech id="31040" comment="VHDL"]. And if there ... » read more

The Week In Review: Design


M&A Mentor acquired Valydate, provider of the VERA schematic integrity analysis tool. Founded in 2010, the Canadian company also offered signal and power integrity and static timing analysis services. Valydate's technology will be integrated with Mentor's Xpedition PCB design flow, though former Valydate CEO Michael Alam says it will continue to serve all EDA environments. Tools Aldec ... » read more

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