The Rise Of Parallelism


Parallel computing is an idea whose time has finally come, but not for the obvious reasons. Parallelism is a computer science concept that is older Moore's Law. In fact, it first appeared in print in a 1958 IBM research memo, in which John Cocke, a mathematician, and Daniel Slotnick, a computer scientist, discussed parallelism in numerical calculations. That was followed eight years later by... » read more

Researchers Learn New Tricks


There is very little EDA research being done in universities today, except for very narrow fields such as [getkc id="33" kc_name="formal verification"]. It has been a steady decline over quite a long period of time. There are several reasons for this. The first is money. Money has to flow into the universities to pay for the research, and this has to lead to some form of prestige for the est... » read more

Avoiding A $7.7B Chip Design Cost


For years, the story about semiconductor development cost and about EDA contributions has been pretty simple. Cost has been, is, and will likely be for a while, the single biggest issue in scaling development for more complex designs. The next big leap for verification productivity will be the close integration of verification and design engines, both vertically and horizontally as I have writt... » read more

54th DAC Program Finalized


A DAC winter meeting held in sunny Mexico isn’t what it’s cracked up to be. (Although we did enjoy the break from this winter storms!) Everybody thinks the Executive Committee members are lounging on the beach enjoying drinks with little umbrellas in them. That couldn’t be further from the truth! In fact, I and 15 other EC members spent most of our February meetings in Puerto Vallar... » read more

HBM Upstages DDR In Bandwidth, Power


For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

Carving Up Verification


Anirudh Devgan, executive vice president and general manager of [getentity id="22032" e_name="Cadence's"] System & Verification Group, sat down with Semiconductor Engineering to discuss the evolution of verification. What follows are excerpts of that conversation. SE: What’s changing in [getkc id="10" kc_name="verification"]? Devgan: Parallelism, greater capacity and multiple engine... » read more

Antenna Design Grows Up


Apple’s iPhone 4 antenna issue represents a classic example of what can go wrong in modern antenna design. Put one in the wrong place, and a seemingly insignificant part can turn a cool new product into a public relations nightmare. Ever since antennas dropped out of sight, most consumers don't give them a second thought. In the 1960s, almost every home had a rooftop antenna. Fast forward ... » read more

The Ultimate Shift Left


Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

Crossing The Chasm: Uniting SoC And Package Verification


Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, and foundries must collaborate to establish consistent and unified automated WLP design and physical verification flows, while introducing minimum disruption to already-existing package design flows.... » read more

Better Code With RTL Linting And CDC Verification


Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

← Older posts