Age Of Acceleration


A shift from the fastest processors to accelerating specific functions is underway, supplanting an era of dark silicon in which one or more processor cores remain in a ready state whenever a single core's performance bogs down. In effect, the dark silicon/multi-core approach is being scrapped for many functions in favor of an accelerator-based microarchitecture that is far more granular. The... » read more

Hardware/Software Tipping Point


It doesn't matter if you believe [getkc id="74" comment="Moore's Law"] has ended or is just slowing down. It is becoming very clear that design in the future will be significant different than it is today. Moore's law allowed the semiconductor industry to reuse design blocks from previous designs, and these were helped along by a new technology node—even if it was a sub-optimal solution. I... » read more

Whatever Happened To HLS?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high-lev... » read more

Embedded FPGA, The Ultimate Accelerator


An embedded FPGA (eFPGA) is an IP core that you integrate into your ASIC or SoC to get the benefits of programmable logic without the cost, but with better latency, throughput, and power characteristics. With an eFPGA, you define the quantity of look-up-tables (LUTs), registers, embedded memory, and DSP blocks. You can also control the aspect ratio, number of I/O ports, making tradeoffs between... » read more

Tech Talk: eFPGA Acceleration


Achronix's Kent Orthner talks about when and why to use embedded FPGAs, and how they co-exist with—and compare to—other processing elements. [youtube vid=TXeIOmo7O9o] » read more

The Week In Review: Design


Tools Mentor Graphics launched the company's third generation data-center friendly emulation platform, Veloce Strato. The emulator has a capacity of 2.5BG when fully loaded, and total capacity can be increased by linking emulators. It has available slots for 64 Advanced Verification Boards (AVBs) and fully loaded consumes up to 50KW (22.7 W/Mgate) of power. Aldec uncorked the latest versi... » read more

The Week In Review: Design


Tools Cadence launched its Sigrity 2017 technology portfolio for PCB power and signal integrity signoff, adding a power topology viewer and editor, library management for power integrity models, and a PCI Express 4.0 compliance kit for checking signal integrity. Memory Spin Transfer Technologies delivered samples of fully functional ST-MRAM (spin transfer magneto-resistive random acces... » read more

Menta Embeds FPGA Programmability


What constitutes a startup can be a matter of the market segment you are going after and the type of product that you are building. Within [getkc id="7" kc_name="EDA"], we often think of the lifetime of a company being just a few years between when an opportunity is identified, to a product being built and getting the first few customers and then getting gobbled up by one of the big three. But ... » read more