Chip Industry Week In Review


SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan AMD took the covers off new AI accelerators for training and inferencing of large language model and high-performance computing workloads. In its announcement, AMD focused heavily on performance leadership in the commercial AI processor space through a combination of architectural changes, better software efficiency, along with some improvements in... » read more

Research Bits: November 14


Solid-state thermal transistor for heat management Researchers from University of California Los Angeles created a stable and fully solid-state thermal transistor that uses an electric field to control a semiconductor device’s heat movement. It is compatible with integrated circuits in semiconductor manufacturing processes. The team’s design incorporates the field effect on charge dynamics... » read more

Chip Industry Talent Shortage Drives Academic Partnerships


Universities around the world are forming partnerships with semiconductor companies and governments to help fill open and future positions, to keep curricula current and relevant, and to update and expand skills for working engineers. Talent shortages repeatedly have been cited as the number one challenge for the chip industry. Behind those concerns are several key drivers, and many more dom... » read more

Blog Review: September 6


Cadence's Reela Samuel listens in as industry experts discuss whether generative AI-powered tools could facilitate the creation of diverse chip types and address talent shortages by creating  a more accessible entry point for those interested in circuit, chip, or system design. Synopsys' Ian Land, Jigesh Patel, and Kenneth Larsen find that the way that today’s government, aerospace, and d... » read more

Chip Industry’s Technical Paper Roundup: July 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=119 /] More Reading Technical Paper Library home » read more

How To Fine-Tune Large-Area Molybdenum Disulfide Atomic Layer Deposition At 150°C


A technical paper titled "Toolbox of Advanced Atomic Layer Deposition Processes for Tailoring Large-Area MoS2 Thin Films at 150 °C" was published by researchers at Eindhoven University of Technology, University of Michigan, and University College Cork. Abstract: "Two-dimensional MoS2 is a promising material for applications, including electronics and electrocatalysis. However, scalable meth... » read more

Week In Review: Semiconductor Manufacturing, Test


The U.S. Commerce Department  launched Chips.gov, a website that covers all aspects of the CHIPS Act, including funding opportunities and job openings. In similar vein, Intel CEO Pat Gelsinger focused on the future of semiconductor manufacturing in America in a talk at MIT. Intel has committed to expanding semiconductor manufacturing in the U.S., including spending an initial $20 billion on ne... » read more

Chip Industry’s Technical Paper Roundup: Apr. 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=93 /]   If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involv... » read more

EUV Lithography: Results of Single Particle Volume Charging Processes in EUV Exposure Environment With Focus On Afterglow Effects


A new technical paper titled "Particle charging during pulsed EUV exposures with afterglow effect" was published by researchers at ASML, ISTEQ B.V., and Eindhoven University of Technology. Abstract "The nanoparticle charging processes along with background spatial-temporal plasma profile have been investigated with 3DPIC simulation in a pulsed EUV exposure environment. It is found that the ... » read more

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