The Week In Review: Design

IP Rambus debuted 3200 Mbps DDR4 PHY, targeted at the data center and networking markets, on the GlobalFoundries FX-14 ASIC platform using the company's 14nm Power Plus (LPP) process. The PHY is DFI 4.0 compatible, and supports 16 – 72-bit interfaces, along with single and multi-rank configurations. Synopsys introduced VIP and UVM source code test suite for Ethernet 200G, supporting 4x5... » read more

The Week In Review: Design/IoT

Tools Aldec updated its emulation and simulation acceleration software package for high speed prototyping boards, adding a SCE-MI Pipes-based flow for streaming large amounts of data, and a 30% speed increase for all emulation modes. Plus, Aldec's mixed-language FPGA design and simulation platform now includes a complete coverage analysis package for FPGA and ASIC designers with the addition... » read more