The Week In Review: Design


M&A PLDA is divesting its Reflex CES brand. The FPGA board maker will become wholly managed by its own management and investment teams. In 2015, Reflex CES took over the hardware businesses of PLDA, including FPGA-based boards and the System-on-Module product lines. Tools Mentor uncorked a new tool for in-system test and diagnosis of automotive ICs. Tessent MissionMode provides infrast... » read more

The Week In Review: Design


IP Rambus unveiled High Bandwidth Memory (HBM) Gen2 PHY developed for GlobalFoundries' FX-14 ASIC platform. The PHY, targeted at networking and data center applications, is fully compliant with the JEDEC HBM2 standard and supports data rates up to 2000 Mbps per data pin, for a total bandwidth of 256 GB/s. Omnitek launched a number of new FPGA-based video IPs, including HDMI2.0 Tx and Rx, ... » read more

The Week In Review: Design


M&A Siemens plans to buy Mentor Graphics for $4.5 billion in cash. The move, if approved by regulators, would greatly expand Siemens’ capabilities in multi-physics design and embedded software for everything from semiconductors to automotive wiring harnesses. The transaction is expected to close in the second quarter of 2017. Tools Mentor Graphics uncorked a new product to measur... » read more

Executive Insight: Charlie Cheng


[getperson id="11073" comment="Charlie Cheng"], CEO of [getentity id="22135" e_name="Kilopass Technology"], sat down with Semiconductor Engineering to talk about the limitations of DRAM, how to get around them, and who's likely to do that. What follows are excerpts of that discussion. SE: What are the top market segments from a [getkc id="22" kc_name="memory"] standpoint? Cheng: The top o... » read more

The Week In Review: Design


IP Rambus debuted 3200 Mbps DDR4 PHY, targeted at the data center and networking markets, on the GlobalFoundries FX-14 ASIC platform using the company's 14nm Power Plus (LPP) process. The PHY is DFI 4.0 compatible, and supports 16 – 72-bit interfaces, along with single and multi-rank configurations. Synopsys introduced VIP and UVM source code test suite for Ethernet 200G, supporting 4x5... » read more

The Week In Review: Design/IoT


Tools Aldec updated its emulation and simulation acceleration software package for high speed prototyping boards, adding a SCE-MI Pipes-based flow for streaming large amounts of data, and a 30% speed increase for all emulation modes. Plus, Aldec's mixed-language FPGA design and simulation platform now includes a complete coverage analysis package for FPGA and ASIC designers with the addition... » read more