Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

The New Face of Formal


Semiconductor engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager R&D, verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"], Normando... » read more

Equivalence Checking


Everyone is consumed by power these days. The less power our devices use, the better—the longer our batteries will last, the more applications we can use simultaneously, the less HVAC capacity is required by the data center, etc. Clock-gating is one widely used technique to save power in ASIC designs. However, clock gating can significantly impact the structural and behavioral elements of the... » read more