Memory Model Verification at the Trisection of Software, Hardware, and ISA (Princeton)


Source: Princeton University, Caroline Trippel, Yatin A. Manerkar, Daniel Lustig*, Michael Pellauer*, Margaret Martonosi *NVIDIA Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for... » read more

Modeling Errors


Raising the abstraction level in increasingly large and complex design requires proxies. In IC world, we think of them in terms of higher abstractions, but the basic premise is that you can’t focus on ever detail without losing sight of the bigger picture, so we build models that can represent those details. Done well, these models are incredibly useful. They save time, make it easier to ... » read more