tag: Everspin Technologies

Week In Review: Design, Low Power
By Jesse Allen - 11 Nov, 2022 - Comments: 0

Chip design Fraunhofer IIS/EAS implemented the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung's 5nm technology. The effort is intended to make chiplets more feasible for products with small and medium-sized production runs and determine the need for additional uniform standards in the future, such as for die-to-die bonding. “As part of t... » read more

CMOS-Embedded STT-MRAM Arrays In 2x nm Nodes For GP-MCU Applications
By GlobalFoundries - 20 Jul, 2017 - Comments: 0

Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS- embedded 40 Mb array. Key features are full a... » read more

Big Memory Shift Ahead
By Brian Bailey - 22 May, 2014 - Comments: 1

System architecture has been driven by the performance of [getkc id="22" kc_name="memory"]. Processor designers would have liked all of the memory be fast [getkc id="92" kc_name="SRAM"], placed on-chip for maximum performance, but that was not an option. Memory had to be fabricated as separate chips and connected via a Printed Circuit Board (PCB). That limited the number of available I/O ports ... » read more

Universal Memories Fall Back To Earth
By Ed Sperling - 20 Sep, 2012 - Comments: 0

By Mark LaPedus Ten years ago, Intel Corp. declared that flash memory would stop scaling at 65nm, prompting the need for a new replacement technology. Thinking the end was near for flash, a number of companies began to develop various next-generation memory types, such as 3D chips, FeRAM, MRAM, phase-change memory (PCM), and ReRAM. Many of these technologies were originally billed as “uni... » read more

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