Pattern Matching In Test And Yield Analysis


By Jonathan Muirhead and Geir Eide It’s no secret that a successful yield ramp directly impacts integrated circuit (IC) product cost and time-to-market. Tools and techniques that help companies ramp to volume faster, while also reducing process and design variability, can be the difference between profit and loss in a competitive market. And while pattern matching technology has been aroun... » read more

Balancing The Cost Of Test


As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

Improve Failure Analysis Success Rate With Layout-Aware Diagnosis


In this whitepaper, we explore how a layout-aware diagnosis is a powerful tool for both failure analysis engineers, who find the root cause of a particular failing die, and for yield engineers, who need sets of diagnosis data to find the systematic yield limiters across the life of the product. Logic-based scan test diagnosis is an established software-based methodology for finding the defec... » read more

Root Cause Deconvolution


Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic advance in diagnosis technology because it reduces suspect area by up to 85% and identifies physical net segments rather than entire logic nets [1-3]. The defect classifications provided by ... » read more