tag: failure analysis

Pressure Builds On Failure Analysis Labs
By Laura Peters - 09 Jan, 2024 - Comments: 0

Failure analysis labs are becoming more fab-like, offering higher accuracy in locating failures and accelerating time-to-market of new devices. These labs historically have been used for deconstructing devices that failed during field use, known as return material authorizations (RMAs), but their role is expanding. They now are becoming instrumental in achieving first silicon and ramping yie... » read more

Applying ML In Failure Analysis
By Anne Meixner - 20 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how increasing complexity in semiconductor and packaging technology is driving shifts in failure analysis methods, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; Mike McIntyre, director of product management in the Enterprise Business Unit at Onto Innovation; Kamran H... » read more

Isolating Critical Data In Failure Analysis
By Anne Meixner - 01 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss traceability and the lack of data needed to perform root cause analysis with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; Mike McIntyre, director of product management in the Enterprise Business Unit at Onto Innovation; Kamran Hakim, ASIC reliability engineer at Teradyne... » read more

Streamlining Failure Analysis Of Chips
By Anne Meixner - 10 Oct, 2023 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss how increasing complexity in semiconductor and packaging technology is driving shifts in failure analysis methods, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; Mike McIntyre, director of product management in the Enterprise Business Unit at Onto Innovation; Kamran Hak... » read more

EDA’s Role Grows For Preventing And Identifying Failures
By Karen Heyman - 08 Jun, 2023 - Comments: 0

The front end of design is becoming more tightly integrated with the back end of manufacturing, driven by the rising cost and impact of failures in advanced chips and critical applications. Ironically, the starting point for this shift is failure analysis (FA), which typically happens when a device fails to yield, or worse, when it is returned due to some problem. In production, that leads t... » read more

GaN Power Devices: Stability, Reliability and Robustness Issues
By Technical Paper Link - 30 Apr, 2023 - Comments: 0

A technical paper titled "Stability, Reliability, and Robustness of GaN Power Devices: A Review" was published by researchers at Virginia Polytechnic Institute and State University, Johns Hopkins University Applied Physics Laboratory, and Kyushu University. "Gallium nitride (GaN) devices are revolutionarily advancing the efficiency, frequency, and form factor of power electronics. However, t... » read more

Silicon Lifecycle Management Advances With Unified Analytics
By Guy Cortez - 25 Apr, 2023 - Comments: 0

In a typical day in the life of a product engineer, they have gone through the requisite wafer sort testing in manufacturing with the next step to assemble the resultant good die into their respective packages. While performing a series of parametric tests during final test, yield issues are encountered and the process of finding the source of the issues begins. Luckily, with access to a good d... » read more

X-Ray Device Alteration (XDA) Of Flip-Chip Packaged FinFET Devices
By Technical Paper Link - 23 Nov, 2022 - Comments: 0

A new technical paper titled "X-Ray Device Alteration Using a Scanning X-Ray Microscope" was published by researchers at NVIDIA and Sigray. "Near Infra-Red (NIR) techniques such as Laser Voltage Probing/Imaging (LVP/I), Dynamic Laser Stimulation (DLS), and Photon Emission Microscopy (PEM) are indispensable for Electrical Fault Isolation/Electrical Failure Analysis (EFI/EFA) of silicon Integr... » read more

Next Steps For Improving Yield
By Laura Peters - 08 Nov, 2022 - Comments: 0

Chipmakers are ramping new tools and methodologies to achieve sufficient yield faster, despite smaller device dimensions, a growing number of systematic defects, immense data volumes, and massive competitive pressure. Whether a 3nm process is ramping, or a 28nm process is being tuned, the focus is on reducing defectivity. The challenge is to rapidly identify indicators that can improve yield... » read more

Better, Faster, And More Efficient Verification With The Power Of AI
By Synopsys - 07 Sep, 2022 - Comments: 0

Verification is often the most challenging part of the chip development process. Verification engineers have to balance quality of results (QOR) with time to results (TTR) and cost of results (COR). AI and ML technologies can play a significant part in increasing QOR, speeding up TTR, and reducing COR. This white paper outlines some of the major challenges for verification, describes how AI pro... » read more

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