FD-SOI Adoption Expands

Fully depleted silicon-on-insulator (FD-SOI) is gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs. For years, [getkc id="220" kc_name="FD-SOI"] has been viewed as an either/or solution targeted at the same markets as bulk [gettech id="31093" c... » read more

5 Takeaways From ISS 2018

At the recent Industry Strategy Symposium (ISS) in Half Moon Bay, Calif., there were a multitude of presentations on a number of subjects. The event, sponsored by SEMI, had presentations on the outlook for ICs and equipment. As part of the program, ISS also discussed the latest business and technology trends. In no particular order, here are my five takeaways from ISS: Ranging forecasts ... » read more

What’s In The Package?

Putting a variety of chips or hardened IP blocks into a package rather than trying to cram them into a single chip continues to gain ground. But it's also creating its own set of issues around verifying and testing these devices. This problem is well understood inside of SoCs, where everything is integrated into a single die. And looked at from a 30,000-foot perspective, packaging is someth... » read more

Packaging Challenges For 2018

The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

Fan-Outs vs. TSVs

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

Reliability Of Embedded Wafer-Level BGA For Automotive Radar Applications

With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

Shortages Hit Packaging Biz

Rising demand for chips is hitting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, leadframes and even some equipment. Spot shortages for some IC packages began showing up earlier this year, but the problem has been growing and spreading since then. Supply imbalances reached a boiling point in the third and fourth quarters of this yea... » read more

Five Trends In IC Packaging

At one time, chip packaging was an afterthought. Chipmakers were more worried about IC design. Packaging was considered a mere commodity, which was simply used to house the design. More recently, though, chip packaging has become a hot topic. The IC design is still important, but packaging is a key part of the solution. In fact, the industry can go down two paths. The traditional way is t... » read more

Litho Options For Panel Fan-out

Several packaging houses are inching closer to production of panel-level fan-out packaging, a next-generation technology that promises to reduce the cost of today‚Äôs fan-out packages. In fact, ASE, Nepes, Samsung and others already have installed the equipment in their panel-level fan-out lines with production slated for 2018 or so. But behind the scenes, panel-level packaging houses contin... » read more

Re-Using IP In Packaging

For the past decade, the promise held forth by advanced packaging was that it would allow chipmakers to mix and match analog and digital IP without worrying about the process node at which they were developed or the physical interactions between components. This is a big deal when it comes to analog. Analog IP doesn't benefit from node shrinking the way digital logic does, and in many cases ... » read more

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