Power Impacting Cost Of Chips


The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

Crossing The Chasm: Uniting SoC And Package Verification


Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, and foundries must collaborate to establish consistent and unified automated WLP design and physical verification flows, while introducing minimum disruption to already-existing package design flows.... » read more

What Next For OSATs


Semiconductor Engineering sat down to discuss IC-packaging and business trends with Tien Wu, chief operating officer at Taiwan’s Advanced Semiconductor Engineering ([getentity id="22930" comment="ASE"]), the world’s largest outsourced semiconductor assembly and test (OSAT) vendor. What follows are excerpts of that conversation. SE: What’s the outlook for the IC industry in 2017? Wu:... » read more

Transferring Skills Getting Harder


Rising complexity in developing chips at advanced nodes, and an almost perpetual barrage of new engineering challenges at each new node, are making it more difficult for everyone involved to maintain consistent skill levels across a growing number of interrelated technologies. The result is that engineers are being forced to specialize, but when they work with other engineers with different ... » read more

Overcoming The Limits Of Scaling


Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

Optimizing Multiple IoT Layers


As the number of connected devices rises, so do questions about how to optimize them for target markets, how to ensure they play nicely together, and how to bring them to market quickly and inexpensively. [getkc id="76" kc_name="IoT"] is broad term that encompasses a lot of disparate pieces for devices, systems, and connected systems. At the highest levels are hardware and software, but with... » read more

7nm Design Success Starts With Multi-Domain Multi-Physics Analysis


Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating volt... » read more

Tech Talk: Embedded Memories


Dave Eggleston, vice president of embedded memory at GlobalFoundries, talks about the pros and cons of new types of embedded memory, including which work best for certain applications and with various advanced packaging options. [youtube vid=7D9zoA9FFIw] » read more

Lower Power Plus Better Performance


The tradeoff between power and performance is becoming less about one versus the other, and more about a dual benefit, as new computing and chip architectures begin rolling out. Neural networking, which is one of the hot buttons for any system that relies on lots of distributed sensors, is essential to get a true picture of what is happening around a car moving down the highway at 65 miles ... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

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